Hitoshi TANAKA


Influence of Polymer Gate Dielectrics on p-Channel and n-Channel Formation of Fluorene-type Polymer Light-emitting Transistors
Hirotake KAJII Masato ISE Hitoshi TANAKA Takahiro OHTOMO Yutaka OHMORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/02/01
Vol. E98-C  No. 2  pp. 139-142
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
polymer light-emitting transistorpolyfluoreneambipolar transportgate dielectric
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Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications
Kouji TSUNODA Akira SATO Hiroko TASHIRO Toshiro NAKANISHI Hitoshi TANAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 608-613
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
system-on-a-chipembedded RAMdirect tunnelingtunnel oxidegate depletion
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InGaP-Channel Field Effect Transistors with High Breakdown Voltage
Naoki HARA Yasuhiro NAKASHA Toshihide KIKKAWA Kazukiyo JOSHIN Yuu WATANABE Hitoshi TANAKA Masahiko TAKIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/10/01
Vol. E84-C  No. 10  pp. 1294-1299
Type of Manuscript:  INVITED PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Hetero-FETs & Their Integrated Circuits
Keyword: 
InGaP-channel FEThigh breakdown voltagehigh operating voltagelow distortion
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Sub-1-µA Dynamic Reference Voltage Generator for Battery-Operated DRAM's
Hitoshi TANAKA Yoshinobu NAKAGOME Jun ETOH Eiji YAMASAKI Masakazu AOKI Kazuyuki MIYAZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 778-783
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
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Stabilization of Voltage Limiter Circuit for High-Density DRAM's Using Pole-Zero Compensation
Hitoshi TANAKA Masakazu AOKI Jun ETOH Masashi HORIGUCHI Kiyoo ITOH Kazuhiko KAJIGAYA Tetsurou MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11  pp. 1333-1343
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
memoryDRAMvoltage limiterpole-zero compensation
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