Hisashi IWAMOTO

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Hisashi IWAMOTO Yasuhiro TERAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2  pp. 262-271
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
CAM, IP lookup, index generation unit, FPGA, 
 Summary | Full Text:PDF
A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application
Hisashi IWAMOTO Yuji YANO Yasuto KURODA Koji YAMAMOTO Kazunari INOUE Ikuo OKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/08/01
Vol. E96-C  No. 8  pp. 1076-1082
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
router, address lookup, power consumption, search engine, TCAM, low power, 
 Summary | Full Text:PDF
Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS
Hisashi IWAMOTO Yuji YANO Yasuto KURODA Koji YAMAMOTO Shingo ATA Kazunari INOUE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/07/01
Vol. E96-B  No. 7  pp. 1819-1825
Type of Manuscript:  PAPER
Category: Network System
Keyword: 
packet buffer, multi FIFO queues, memory controller, quality services, 
 Summary | Full Text:PDF
A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme
Hisashi IWAMOTO Naoya WATANABE Akira YAMAZAKI Seiji SAWADA Yasumitsu MURAI Yasuhiro KONISHI Hiroshi ITOH Masaki KUMANOYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1328-1333
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
synchronous DRAM, SDRAM, high speed DRAM, multiple-register, 
 Summary | Full Text:PDF