Hisakazu KOTANI


A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs
Hironori AKAMATSU Toru IWATA Hiroyuki YAMAUCHI Hisakazu KOTANI Akira MATSUZAWA Hiro YAMAMOTO Takashi HIRATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1572-1577
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
multiple-threshold1-voltMT-CMOSdata storage circuitSRAMvirtual power lineintermittent connection
 Summary | Full Text:PDF(633KB)

Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM
Masanori FUKUMOTO Yasushi NAITO Kazuhiro MATSUYAMA Hisashi OGAWA Koji MATSUOKA Takashi HORI Hiroyuki SAKAI Ichiro NAKAO Hisakazu KOTANI Hiroshi IWASAKI Michihiro INOUE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 818-826
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
 Summary | Full Text:PDF(1MB)