IEICE Trans

Hiroyuki YAMAUCHI

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI Yasue YAMAMOTO Masanori SHIRAHAMA Toshiaki KAWASAKI Ryuji NISHIHARA Shinichi SUMI Yasuhiro AGATA Hirohito KIKUKAWA Hiroyuki YAMAUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/05/01 Vol. E90-C No. 5 pp. 1129-1137 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: non-volatile memory, single poly gate, differential cell, CMOS logic process, System-on-Chip (SoC),
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A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 749-757 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: SRAM, 1R/1W-SRAM, disturbed access, SNM, write margin, cell current,
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A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V_th) Variation Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1526-1534 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: SRAM, cell terminal biasing, differential cell terminal, SNM, write margin, disturb,
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0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier Toshikazu SUZUKI Yoshinobu YAMAGAMI Ichiro HATANAKA Akinori SHIBAYAMA Hironori AKAMATSU Hiroyuki YAMAUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 630-638 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Memory Keyword: SRAM, low-voltage, wide-voltage, SoC,
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A Rewritable CMOS-FUSE for System-on-Chip with a Differential Cell Architecture in a 0.13 µm CMOS Logic Process Hiroyuki YAMAUCHI Yasuhiro AGATA Masanori SHIRAHAMA Toshiaki KAWASAKI Ryuji NISHIHARA Kazunari TAKAHASHI Hirohito KIKUKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/10/01 Vol. E87-C No. 10 pp. 1664-1672 Type of Manuscript: Special Section PAPER (Special Section on New Era of Nonvolatile Memories) Category: CMOS Fuse Keyword: nonvolatile memory, data retention, fuse, CMOS compatible,
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A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs Hironori AKAMATSU Toru IWATA Hiroyuki YAMAUCHI Hisakazu KOTANI Akira MATSUZAWA Hiro YAMAMOTO Takashi HIRATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/25 Vol. E80-C No. 12 pp. 1572-1577 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: multiple-threshold, 1-volt, MT-CMOS, data storage circuit, SRAM, virtual power line, intermittent connection,
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Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells Toru IWATA Hiroyuki YAMAUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/25 Vol. E79-C No. 12 pp. 1707-1712 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: DRAM, data retention, memory-cell leakage current,
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An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI'S Hiroyuki YAMAUCHI Hironori AKAMATSU Tsutomu FUJITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/06/25 Vol. E78-C No. 6 pp. 671-679 Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995)) Category: Keyword:
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A Low Power Bus Architecture with Local and Global Charge-Recycling Bus Techniques for Battery-Operated Ultra-High Data Rate ULSI's Hiroyuki YAMAUCHI Hironori AKAMATSU Tsutomu FUJITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/25 Vol. E78-C No. 4 pp. 394-403 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: Digital Circuits Keyword: charge-recycling, low-power, bus-architecture, small-swing, ultra-high-data-rate,
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High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM Toshikazu SUZUKI Toru IWATA Hironori AKAMATSU Akihiro SAWADA Toshiaki TSUJI Hiroyuki YAMAUCHI Takashi TANIGUCHI Tsutomu FUJITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 pp. 1334-1342 Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: DRAM Keyword: DRAM, cycle time, battery operating, high speed,
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