Hiroyuki TOMIYAMA


ILP-Based Scheduling for Parallelizable Tasks
Kana SHIMADA Shogo KITANO Ittetsu TANIGUCHI Hiroyuki TOMIYAMA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1503-1505
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
task scheduling; integer linear programming
 Summary | Full Text:PDF

Static Mapping of Parallelizable Tasks under Deadline Constraints
Yining XU Ittetsu TANIGUCHI Hiroyuki TOMIYAMA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1500-1502
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
task mappingmanycore embedded systemsinteger linear programming
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A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers
Takahiro YAMAMOTO Ittetsu TANIGUCHI Hiroyuki TOMIYAMA Shigeru YAMASHITA Yuko HARA-AZUMI 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1496-1499
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
approximate computingarray multipliersSMT solver
 Summary | Full Text:PDF

Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems
Yining XU Yang LIU Junya KAIDA Ittetsu TANIGUCHI Hiroyuki TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1417-1419
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
application mappingmanycore embedded systemsinteger linear programming
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An Integrated Framework for Energy Optimization of Embedded Real-Time Applications
Hideki TAKASE Gang ZENG Lovic GAUTHIER Hirotaka KAWASHIMA Noritoshi ATSUMI Tomohiro TATEMATSU Yoshitake KOBAYASHI Takenori KOSHIRO Tohru ISHIHARA Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2477-2487
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
energy optimizationcompilerprofilerreal-time operating systemsembedded systems
 Summary | Full Text:PDF

Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs
Ittetsu TANIGUCHI Junya KAIDA Takuji HIEDA Yuko HARA-AZUMI Hiroyuki TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/11/01
Vol. E97-D  No. 11  pp. 2827-2834
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
many-core SoCsapplication mappingsystem-level designembedded systems
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Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path
Ittetsu TANIGUCHI Kohei AOKI Hiroyuki TOMIYAMA Praveen RAGHAVAN Francky CATTHOOR Masahiro FUKUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2  pp. 606-615
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
design space explorationarchitecture explorationvery long instruction-set word (VLIW) processorgenetic algorithm (GA)
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Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs
Junya KAIDA Yuko HARA-AZUMI Takuji HIEDA Ittetsu TANIGUCHI Hiroyuki TOMIYAMA Koji INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/10/01
Vol. E96-D  No. 10  pp. 2268-2271
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
many-core SoCsapplication mappingsystem-level designembedded systems
 Summary | Full Text:PDF

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs
Krzysztof JOZWIK Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 345-353
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
dynamic partial reconfigurationhardware multitasking
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Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems
Hideki TAKASE Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/10/01
Vol. E94-A  No. 10  pp. 1954-1964
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
scratch-pad memoryenergy optimizationcompilercode allocationmulti-task systems
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Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
Yuki ANDO Seiya SHIBATA Shinya HONDA Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2509-2516
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
system-level designhardware sharingdesign space explorationMPSoC
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Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems
Tetsuo YOKOYAMA Gang ZENG Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/10/01
Vol. E93-D  No. 10  pp. 2737-2746
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
battery-aware voltage schedulingdynamic voltage scalinglow powerreal-time systems
 Summary | Full Text:PDF

Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
Yuko HARA Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/02/01
Vol. E93-A  No. 2  pp. 488-499
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
behavioral synthesisfunction-level partitioninginteger programming problem
 Summary | Full Text:PDF

Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model
Shan DING Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/07/01
Vol. E92-D  No. 7  pp. 1412-1420
Type of Manuscript:  PAPER
Category: System Programs
Keyword: 
I/O blockingmulti-frame task modelschedulability analysislaxitygenetic algorithm
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High-Level Synthesis of Software Function Calls
Masanari NISHIMURA Nagisa ISHIURA Yoshiyuki ISHIMORI Hiroyuki KANBARA Hiroyuki TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3556-3558
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesisCCAPhardware/software co-designC-based design
 Summary | Full Text:PDF

An Effective GA-Based Scheduling Algorithm for FlexRay Systems
Shan DING Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/08/01
Vol. E91-D  No. 8  pp. 2115-2123
Type of Manuscript:  PAPER
Category: System Programs
Keyword: 
real-time systemsdistributed embedded systemsFlexRaygenetic algorithm
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Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
Yuko HARA Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA Katsuya ISHII 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2853-2862
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
behavioral synthesisfunction-level partitioninginteger programming problem
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Function Call Optimization for Efficient Behavioral Synthesis
Yuko HARA Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/09/01
Vol. E90-A  No. 9  pp. 2032-2036
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
behavioral synthesisfunction callsinteger programming problem
 Summary | Full Text:PDF

An RTOS-Based Design and Validation Methodology for Embedded Systems
Hiroyuki TOMIYAMA Shin-ichiro CHIKADA Shinya HONDA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/09/01
Vol. E88-D  No. 9  pp. 2205-2208
Type of Manuscript:  LETTER
Category: System Programs
Keyword: 
RTOScosimulationembedded systems
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RTOS-Centric Cosimulator for Embedded System Design
Shinya HONDA Takayuki WAKABAYASHI Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3030-3035
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
RTOScosimulationembedded systems
 Summary | Full Text:PDF

Impacts of Compiler Optimizations on Address Bus Energy: An Empirical Study
Hiroyuki TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/10/01
Vol. E87-A  No. 10  pp. 2815-2820
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
compiler optimizationembedded systemslow energybus encoding
 Summary | Full Text:PDF

ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts
Hiroyuki TOMIYAMA Nikil DUTT 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/06/01
Vol. E87-D  No. 6  pp. 1582-1587
Type of Manuscript:  LETTER
Category: System Programs
Keyword: 
cache-related preemption delayreal-time systemsembedded softwareprogram path analysis
 Summary | Full Text:PDF

Memory Data Organization for Low-Energy Address Buses
Hiroyuki TOMIYAMA Hiroaki TAKADA Nikil D. DUTT 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 606-612
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
compilersembedded processorsmemory data organizationlow energybus encoding
 Summary | Full Text:PDF

Module Selection Using Manufacturing Information
Hiroyuki TOMIYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2576-2584
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-level Synthesis
Keyword: 
high-level synthesismodule selectionmanufacturabilityyield
 Summary | Full Text:PDF

Language and Compiler for Optimizing Datapath Widths of Embedded Systems
Akihiko INOUE Hiroyuki TOMIYAMA Takanori OKUMA Hiroyuki KANBARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2595-2604
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design
Keyword: 
embedded system designhardware/software codesignretargetable compiler
 Summary | Full Text:PDF

Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches
Hiroyuki TOMIYAMA Tohru ISHIHARA Akihiko INOUE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2621-2629
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Compiler
Keyword: 
compiler optimizationinstruction schedulinglow powercaches
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Soft-Core Processor Architecture for Embedded System Design
Eko Fajar NURPRASETYO Akihiko INOUE Hiroyuki TOMIYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1416-1423
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
scalable processordatapath widthmemory
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Embedded System Cost Optimization via Data Path Width Adjustment
Barry SHACKLEFORD Mitsuhiro YASUDA Etsuko OKUSHI Hisao KOIZUMI Hiroyuki TOMIYAMA Akihiko INOUE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 974-981
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High Level Synthesis
Keyword: 
embedded systemssystem on chipCPUmemory
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Satsuki: An Integrated Processor Synthesis and Compiler Generation System
Barry SHACKLEFORD Mitsuhiro YASUDA Etsuko OKUSHI Hisao KOIZUMI Hiroyuki TOMIYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1373-1381
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Hardware-Software Codesign
Keyword: 
computer aided designsystem designprocessor designcompiler generation
 Summary | Full Text:PDF