Hiroyuki OKUHATA

Performance Prediction of Wireless Vital Data Collection System for Exercisers by a Network Simulator
Takuma HAMAGAMI Shinsuke HARA Hiroyuki YOMO Ryusuke MIYAMOTO Yasutaka KAWAMOTO Takunori SHIMAZAKI Hiroyuki OKUHATA 
Publication:   
Publication Date: 2020/06/01
Vol. E103-B  No. 6  pp. 653-661
Type of Manuscript:  Special Section PAPER (Special Section on Information and Communication Technology for IoT/CPS in Medicine and Healthcare)
Category: 
Keyword: 
wireless vital sensor nodes, data collection node, network simulator, experiment involving subjects, 
 Summary | Full Text:PDF
An Architecture for Real-Time Retinex-Based Image Enhancement and Haze Removal and Its FPGA Implementation
Dabwitso KASAUKA Kenta SUGIYAMA Hiroshi TSUTSUI Hiroyuki OKUHATA Yoshikazu MIYANAGA 
Publication:   
Publication Date: 2019/06/01
Vol. E102-A  No. 6  pp. 775-782
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
real time processing, FPGA, Retinex-based image enhancement, haze removal, 
 Summary | Full Text:PDF
Real-Time Vital Monitoring for Persons during Exercises — Solutions and Challenges —
Shinsuke HARA Hiroyuki OKUHATA Takashi KAWABATA Hajime NAKAMURA Hiroyuki YOMO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2016/03/01
Vol. E99-B  No. 3  pp. 556-564
Type of Manuscript:  INVITED PAPER (Special Section on Information and Communication Technology for Healthcare and Medical Applications in Conjunction with Main Topics of ISMICT2015)
Category: 
Keyword: 
vital sensing, wireless transmission, heart rate, body temperature, energy expenditure, 
 Summary | Full Text:PDF
Design of Ogg Vorbis Decoder System for Embedded Platform
Atsushi KOSAKA Hiroyuki OKUHATA Takao ONOYE Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/08/01
Vol. E88-A  No. 8  pp. 2124-2130
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from the 19th Symposium on Signal Processing)
Category: VLSI Design Technology and CAD
Keyword: 
embedded system design, Ogg Vorbis decoder, MDCT, residue decoding process, 
 Summary | Full Text:PDF
A Low-Power DSP Core Architecture for Low Bitrate Speech Codec
Hiroyuki OKUHATA Morgan H. MIKI Takao ONOYE Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/08/25
Vol. E81-A  No. 8  pp. 1616-1621
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
G. 723. 1, VLSI, DSP, low-power, speech codec, 
 Summary | Full Text:PDF