Hiroyuki MORINAKA

A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Koichiro MASHIKO Tadashi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 915-924
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Logic
Keyword: 
 Summary | Full Text:PDF(933.5KB)
A 2.6-ns 64-b Fast and Small CMOS Adder
Hiroyuki MORINAKA Hiroshi MAKINO Yasunobu NAKASE Hiroaki SUZUKI Koichiro MASHIKO Tadashi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4  pp. 530-537
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
addition, carry look-ahead adder, binary look-ahead adder, carry select, modified carry select, CMOS, VLSI, 
 Summary | Full Text:PDF(642.3KB)
A Design of High-Speed 4-2 Compressor for Fast Multiplier
Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Hirofumi SHINOHARA Koichiro MASHIKO Tadashi SUMI Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4  pp. 538-548
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
4-2 compressor, multiplier, redundant binary, transmission gate, CMOS circuit, 
 Summary | Full Text:PDF(1012.7KB)