Hiroyuki MIYAUCHI


A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space
Mineo KANEKO Hiroyuki MIYAUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/12/25
Vol. E79-D  No. 12  pp. 1676-1689
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
VLSI array processorsystolic arrayfault tolerancecommunication linkdependence graph
 Summary | Full Text:PDF(1.1MB)

Fault Tolerant Non-regular Digital Signal Processing Based on Computation Tree Block Decomposition
Mineo KANEKO Hiroyuki MIYAUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/09/25
Vol. E77-A  No. 9  pp. 1535-1545
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
fault toleranceon-line error correctionsignal flow graphDSP algorithm
 Summary | Full Text:PDF(955.2KB)