Hiroyuki KURINO

A Power-Down Circuit Scheme Using Data-Preserving Complementary Pass Transistor Flip-Flop for Low-Power High-Performance Multi-Threshold CMOS LSI
Ki-Tae PARK Tomokatsu MIZUKUSA Hyo-Sig WON Kyu-Myung CHOI Jeong-Taek KONG Hiroyuki KURINO Mitsumasa KOYANAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 645-648
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
low-power, MTCMOS, data-preserving, complementary pass transistor, power-down circuit scheme, 
 Summary | Full Text:PDF
A Low-Power Edge-Triggered and Logic-Embedded Flip-Flop Using Complementary Pass Transistor Circuit
Ki-Tae PARK Tomokatsu MIZUKUSA Hyo-Sig WON Hiroyuki KURINO Mitsumasa KOYANAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 640-644
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
low-power, flip-flop, logic-embedded, edge-triggered, 
 Summary | Full Text:PDF
Design and Evaluation of a High Speed Routing Lookup Architecture
Jun ZHANG JeoungChill SHIM Hiroyuki KURINO Mitsumasa KOYANAGI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2004/03/01
Vol. E87-B  No. 3  pp. 406-412
Type of Manuscript:  Special Section PAPER (Special Section on Internet Technology IV)
Category: Implementation and Operation
Keyword: 
IP routing, selective binary search algorithm, pipelined architecture, cache, 
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Biologically Inspired Vision Chip with Three Dimensional Structure
Hiroyuki KURINO Yoshihiro NAKAGAWA Tomonori NAKAMURA Yusuke YAMADA Kang-Wook LEE Mitsumasa KOYANAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/12/01
Vol. E84-C  No. 12  pp. 1717-1722
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Systems with New Concepts)
Category: 
Keyword: 
biologically inspired system, neuromorphic system, three dimensional LSI, vision chip, 
 Summary | Full Text:PDF
Evaluation of Shared DRAM for Parallel Processor System with Shared Memory
Hiroyuki KURINO Keiichi HIRANO Taizo ONO Mitsumasa KOYANAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2655-2660
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: LSI Architecture
Keyword: 
multiport memory, shared memory, parallel processor system, DRAM, 
 Summary | Full Text:PDF