Hiroshige FUJII

Hiding Data Cache Latency with Load Address Prediction
Toshinori SATO Hiroshige FUJII Seigo SUZUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/11/25
Vol. E79-D  No. 11  pp. 1523-1532
Type of Manuscript:  PAPER
Category: Computer Systems
RISCcache memoryload-use hazardload latencyaddress prediction
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Implementation Techniques for Fast OBDD Dynamic Variable Reordering
Hiroshige FUJII 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1729-1734
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
ordered binary decision diagramsdynamic variable reorderingsifting algorithm
 Summary | Full Text:PDF(513.3KB)

Performance Evaluation of a Processing Element for an On-Chip Multiprocessor
Masafumi TAKAHASHI Hiroshige FUJII Emi KANEKO Takeshi YOSHIDA Toshinori SATO Hiroyuki TAKANO Haruyuki TAGO Seigo SUZUKI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1092-1100
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
multiprocessorshared FPUon-chip cacheprefetch
 Summary | Full Text:PDF(878.8KB)