Hiroshi TSUTSUI


An Architecture for Real-Time Retinex-Based Image Enhancement and Haze Removal and Its FPGA Implementation
Dabwitso KASAUKA Kenta SUGIYAMA Hiroshi TSUTSUI Hiroyuki OKUHATA Yoshikazu MIYANAGA 
Publication:   
Publication Date: 2019/06/01
Vol. E102-A  No. 6  pp. 775-782
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
real time processingFPGARetinex-based image enhancementhaze removal
 Summary | Full Text:PDF(4.5MB)

A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis
Takashi IMAGAWA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 454-462
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
soft errorsingle event upsettriple modular redundancyreliabilitysimulated annealing
 Summary | Full Text:PDF(1.4MB)

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
Hiroshi YUASA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 473-481
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
statistical static timing analysisdelay distributionslew ratefield-programmable gate arrayMersenne Twister
 Summary | Full Text:PDF(1.3MB)

A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits
Junya KAWASHIMA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2242-2250
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
subthreshold operationprocess variationminimum operation voltage estimationenergy minimizationyield maximization
 Summary | Full Text:PDF(837.1KB)

Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method
Hiromitsu AWANO Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2272-2283
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
random telegraph noiseBayesian estimationMarkov chain Monte Carlodevice characterizationsource separationstatistical machine learning
 Summary | Full Text:PDF(3.3MB)

Efficient Memory Organization Framework for JPEG2000 Entropy Codec
Hiroki SUGANO Takahiko MASUZAKI Hiroshi TSUTSUI Takao ONOYE Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/08/01
Vol. E92-A  No. 8  pp. 1970-1977
Type of Manuscript:  Special Section PAPER (Special Section on Signal Processing)
Category: Realization
Keyword: 
JPEG2000entropy codechardwarememory organization
 Summary | Full Text:PDF(600KB)

Stochastic Pedestrian Tracking Based on 6-Stick Skeleton Model
Ryusuke MIYAMOTO Jumpei ASHIDA Hiroshi TSUTSUI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/03/01
Vol. E90-A  No. 3  pp. 606-617
Type of Manuscript:  Special Section PAPER (Special Section on Multimedia and Mobile Signal Processing)
Category: Image
Keyword: 
pedestrian trackingparticle filterskeletondistance transformation
 Summary | Full Text:PDF(2MB)

LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression
Hiroshi TSUTSUI Akihiko TOMITA Shigenori SUGIMOTO Kazuhisa SAKAI Tomonori IZUMI Takao ONOYE Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2681-2689
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: FPGA Systhesis
Keyword: 
reconfigurable logicprogrammable logicsystem architecture and designlogic synthesissum of products
 Summary | Full Text:PDF(691.5KB)