Hiroshi TOYOSHIMA

A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM
Hideharu YAHATA Yoji NISHIO Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Atsushi HIRAISHI Yoshitaka KINOSHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 557-565
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
CMOS, high speed, cache SRAM, chip floor plan, sense amplifier, output register, setup/hold time, 
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A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers
Koichiro ISHIBASHI Koichi TAKASUGI Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Toshiaki YAMANAKA Akira FUKAMI Naotaka HASHIMOTO Nagatoshi OHKI Akihiro SHIMIZU Takashi HASHIMOTO Takahiro NAGANO Takashi NISHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 728-734
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
 Summary | Full Text:PDF
A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's
Koichiro ISHIBASHI Katsuro SASAKI Toshiaki YAMANAKA Hiroshi TOYOSHIMA Fumio KOJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 572-575
Type of Manuscript:  Special Section LETTER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF