IEICE SEARCH SYSTEM

Hiroshi TAKAHASHI

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines Hiroyuki YOTSUYANAGI Kotaro ISE Masaki HASHIZUME Yoshinobu HIGAMI Hiroshi TAKAHASHI
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2842-2850 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: resistive open, small delay fault, adjacent line, delay variation, anomaly detection,
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A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line Yoshinobu HIGAMI Senling WANG Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA
Publication: Publication Date: 2017/09/01 Vol. E100-D No. 9 pp. 2224-2227 Type of Manuscript: LETTER Category: Dependable Computing Keyword: fault diagnosis, bridging faults, clock lines,
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Design and Experimental Evaluation of 60GHz Multiuser Gigabit/s Small Cell Radio Access Based on IEEE 802.11ad/WiGig Koji TAKINAMI Naganori SHIRAKATA Masashi KOBAYASHI Tomoya URUSHIHARA Hiroshi TAKAHASHI Hiroyuki MOTOZUKA Masataka IRIE Masayuki SHIMIZU Yuji TOMISAWA Kazuaki TAKAHASHI
Publication: Publication Date: 2017/07/01 Vol. E100-B No. 7 pp. 1075-1085 Type of Manuscript: Special Section PAPER (Special Section on Smart Radio and Its Applications in Conjunction with Main Topics of SmartCom) Category: Terrestrial Wireless Communication/Broadcasting Technologies Keyword: IEEE 802.11ad, WiGig, 60 GHz, small cell, heterogeneous network, 5G cellular network,
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A 60 GHz Hybrid Analog/Digital Beamforming Receiver with Interference Suppression for Multiuser Gigabit/s Radio Access Koji TAKINAMI Hiroyuki MOTOZUKA Tomoya URUSHIHARA Masashi KOBAYASHI Hiroshi TAKAHASHI Masataka IRIE Takenori SAKAMOTO Yohei MORISHITA Kenji MIYANAGA Takayuki TSUKIZAWA Noriaki SAITO Naganori SHIRAKATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/07/01 Vol. E99-C No. 7 pp. 856-865 Type of Manuscript: PAPER Category: Microwaves, Millimeter-Waves Keyword: IEEE 802.11ad, WiGig, 60 GHz, direct conversion, CMOS, beamforming, interference suppression, interference rejection combining,
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FOREWORD Hiroshi TAKAHASHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 pp. 1905-1906 Type of Manuscript: FOREWORD Category: Keyword:
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Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/06/01 Vol. E96-D No. 6 pp. 1323-1331 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test generation, fault simulation, clock line, delay fault,
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Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool Yoshinobu HIGAMI Satoshi OHNO Hironori YAMAOKA Hiroshi TAKAHASHI Yoshihiro SHIMIZU Takashi AIKYO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/04/01 Vol. E95-D No. 4 pp. 1093-1100 Type of Manuscript: PAPER Category: Dependable Computing Keyword: fault diagnosis, test generation, transition faults, stuck-at ATPG,
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Compact and Athermal DQPSK Demodulator with Silica-Based Planar Lightwave Circuit Yusuke NASU Yohei SAKAMAKI Kuninori HATTORI Shin KAMEI Toshikazu HASHIMOTO Takashi SAIDA Hiroshi TAKAHASHI Yasuyuki INOUE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/07/01 Vol. E93-C No. 7 pp. 1191-1198 Type of Manuscript: PAPER Category: Optoelectronics Keyword: differential quadrature phase-shift keying (DQPSK), Mach-Zehnder, Delay-line interferometer, optical planar waveguides,
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Addressing Defect Coverage through Generating Test Vectors for Transistor Defects Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3128-3135 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: test generation, transistor defects, stuck-at tests, defect coverage,
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Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3506-3513 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: fault simulation, test generation, stuck-open faults, stuck-at tests, defect coverage,
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Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 690-699 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Defect-Based Testing Keyword: transistor short, fault simulation, test generation, stuck-at test tool,
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Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information Yuzo TAKAMATSU Hiroshi TAKAHASHI Yoshinobu HIGAMI Takashi AIKYO Koji YAMAZAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 675-682 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: diagnosis, fault model, fault location, fault simulation, combinational circuits, pass/fail information,
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Post-BIST Fault Diagnosis for Multiple Faults Hiroshi TAKAHASHI Yoshinobu HIGAMI Shuhei KADOYAMA Yuzo TAKAMATSU Koji YAMAZAKI Takashi AIKYO Yasuo SATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 771-775 Type of Manuscript: Special Section LETTER (Special Section on Test and Verification of VLSIs) Category: Keyword: post-BIST fault diagnosis, multiple stuck-at faults, combinational circuits, pass/fail information,
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Low-Phase Noise Photonic Millimeter-Wave Generator Using an AWG Integrated with a 3-dB Combiner Akihiko HIRATA Hiroyoshi TOGO Naofumi SHIMIZU Hiroshi TAKAHASHI Katsunari OKAMOTO Tadao NAGATSUMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/07/01 Vol. E88-C No. 7 pp. 1458-1464 Type of Manuscript: Special Section PAPER (Special Section on Recent Technologies of Microwave and Millimeter-Wave Devices Focusing on Miniaturization and Advancement in Performance with Their Applications) Category: Millimeter-Wave Technologies Keyword: photonic millimeter-wave generator, planar lightwave circuit, arrayed-waveguide grating, phase noise,
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A 1.5 V, 200 MHz, 400 MIPS, 188 µA/MHz and 1.2 V, 300 MHz, 600 MIPS, 169 µA/MHz Digital Signal Processor Core for 3G Wireless Applications Hiroshi TAKAHASHI Shigeshi ABIKO Kenichi TASHIRO Kaoru AWAKA Yutaka TOYONOH Rimon IKENO Shigetoshi MURAMATSU Yasumasa IKEZAKI Tsuyoshi TANAKA Akihiro TAKEGAMA Hiroshi KIMIZUKA Hidehiko NITTA Miki KOJIMA Masaharu SUZUKI James Lowell LARIMER
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 491-501 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: 200 MHz, 300 MHz, 400 MIPS, 600 MIPS, high-speed, low-power, fixed point DSP, 130 nm,
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An Alternative Test Generation for Path Delay Faults by Using N_i-Detection Test Sets Hiroshi TAKAHASHI Kewal K. SALUJA Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2650-2658 Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing) Category: Test Keyword: test generation, path delay faults N-propagation test-pair set, combinational circuits,
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High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors Hiroshi TAKAHASHI Rimon IKENO Yutaka TOYONOH Akihiro TAKEGAMA Yasumasa IKEZAKI Tohru URASAKI Hitoshi SATOH Masayasu ITOIGAWA Yoshinari MATSUMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 589-596 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Circuit Design Keyword: high speed, low power, fixed point DSP, 160 MHz, 0.18 µm,
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Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1515-1525 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test and Diagnosis for Timing Faults Keyword: diagnosis, crosstalk fault, fault simulation, sequential circuit,
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Process Characterization and Optimization for a Novel Oxide-Free Insulated Gate Structure for InP MISFETs Having Silicon Interface Control Layer Hiroshi TAKAHASHI Masatsugu YAMADA Yong-Gui XIE Seiya KASAI Hideki HASEGAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/10/01 Vol. E84-C No. 10 pp. 1344-1349 Type of Manuscript: Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000)) Category: Hetero-FETs & Their Integrated Circuits Keyword: InP, MISFET, XPS, C-V,
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Fabrication and Characterization of InGaAs/InAlAs Insulated Gate Pseudomorphic HEMTs Having a Silicon Interface Control Layer Yong-Gui XIE Seiya KASAI Hiroshi TAKAHASHI Chao JIANG Hideki HASEGAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/10/01 Vol. E84-C No. 10 pp. 1335-1343 Type of Manuscript: Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000)) Category: Hetero-FETs & Their Integrated Circuits Keyword: insulated gate, PHEMT, InGaAs, interface control, Fermi level pinning,
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Design of C-Testable Modified-Booth Multipliers Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/10/25 Vol. E83-D No. 10 pp. 1868-1878 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: multiplier, modified Booth Algorithm, design for testability (DFT), C-testable design,
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Hybrid External Cavity Lasers Composed of Spot-Size Converter Integrated LDs and UV Written Bragg Gratings in a Planar Lightwave Circuit on Si Takuya TANAKA Hiroshi TAKAHASHI Yoshinori HIBINO Toshikazu HASHIMOTO Akira HIMENO Yasufumi YAMADA Yuichi TOHMORI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/06/25 Vol. E83-C No. 6 pp. 875-883 Type of Manuscript: Special Section PAPER (Special Issue on Advanced Optical Devices for Next Generation High-Speed Communication Systems and Photonic Networks) Category: WDM Network Devices Keyword: external cavity laser, hybrid integration, grating, multiwavelength laser, PLC,
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A 1.2 V, 30 MIPS, 0.3 mA/MIPS and 200 MIPS, 0.58 mA/MIPS Digital Signal Processors Hiroshi TAKAHASHI Shintaro MIZUSHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/25 Vol. E83-C No. 2 pp. 179-185 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: high speed, super low power, MIPS, fixed point DSP, pocket implant, D flip-flop, VIA-2 ROM, 1.2 V, 200 MIPS,
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Diagnosing Delay Faults in Combinational Circuits Under the Ambiguous Delay Model Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/12/25 Vol. E82-D No. 12 pp. 1563-1571 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: combinational circuit, ambiguous delay model, multiple fault diagnosis, path-tracing method,
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A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits Hiroshi TAKAHASHI Kwame Osei BOATENG Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/11/25 Vol. E82-D No. 11 pp. 1466-1473 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: combinational circuit, marginal chip, gate delay fault, test generation, test with linearity property,
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Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 706-715 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Fault Diagnosis Keyword: combinational circuit, fault diagnosis, multiple delay fault, diagnostic rules, path-tracing method, test-pairs for marginal delays,
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A 100 MIPS High Speed and Low Power Digital Signal Processor Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuji OZAWA Kenichi TASHIRO Shigetoshi MURAMATSU Masahiro FUSUMADA Akemi TODOROKI Youichi TANAKA Masayasu ITOIGAWA Isao MORIOKA Hiroyuki MIZUNO Miki KOJIMA Giovanni NASO Emmanuel EGO Frank CHIRAT
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/25 Vol. E80-C No. 12 pp. 1546-1552 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: 100 MIPS, digital signal processing, high speed, low power, CPU,
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A Method of Multiple Fault Diagnosis in Sequential Circuits by Sensitizing Sequence Pairs Nobuhiro YANAGIDA Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/01/25 Vol. E80-D No. 1 pp. 28-37 Type of Manuscript: Special Section PAPER (Special Issue on Fault-Tolerant Computing) Category: Testing/Checking Keyword: sequential circuits, circuit level diagnosis, sensitizing sequence pairs, deduction algorithm, suspected/candidate faults,
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A Circuit Library for Low Power and High Speed Digital Signal Processor Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuni OZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/12/25 Vol. E78-C No. 12 pp. 1717-1725 Type of Manuscript: Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia) Category: Keyword: low power, high speed, low cost, GSM, PDC, NADC, digital signal processing, personal communication, 50 MIPS, CPU,
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A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects Xiangqiu YU Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-D No. 7 pp. 822-829 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: test generation, combinational circuits, redundant faults, delay effect, extended seven-valued calculus,
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Improved Forward Test Generation of Sequential Circuits Using Variable-Length Time Frames Yuzo TAKAMATSU Taijiro OGAWA Hiroshi TAKAHASHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/25 Vol. E76-D No. 7 pp. 832-836 Type of Manuscript: Special Section LETTER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: forward test generation, sequential circuits, variable-length time frames, state escaping,
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A Method of Generating Tests for Combinational Circuits with Multiple Faults Hiroshi TAKAHASHI Nobukage IUCHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/07/25 Vol. E75-D No. 4 pp. 569-576 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: multiple faults, combinational circuits, test generation, robust tests,
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Fluorine Doping Levels in the Low-Pressure PCVD Process Ryoji SETAKA Hiroshi TAKAHASHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1984/06/25 Vol. E67-E No. 6 pp. 333-334 Type of Manuscript: LETTER Category: Optical and Quantum Electronics Keyword:
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