| Hiroshi TAKAHASHI
|
|
|
|
|
|
|
|
|
|
|
FOREWORD Hiroshi TAKAHASHI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D
No. 9
pp. 1905-1906
Type of Manuscript:
FOREWORD Category: Keyword:
| | Summary | Full Text:PDF | |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A 1.5 V, 200 MHz, 400 MIPS, 188 µA/MHz and 1.2 V, 300 MHz, 600 MIPS, 169 µA/MHz Digital Signal Processor Core for 3G Wireless Applications Hiroshi TAKAHASHI Shigeshi ABIKO Kenichi TASHIRO Kaoru AWAKA Yutaka TOYONOH Rimon IKENO Shigetoshi MURAMATSU Yasumasa IKEZAKI Tsuyoshi TANAKA Akihiro TAKEGAMA Hiroshi KIMIZUKA Hidehiko NITTA Miki KOJIMA Masaharu SUZUKI James Lowell LARIMER | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C
No. 4
pp. 491-501
Type of Manuscript:
Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: 200 MHz, 300 MHz, 400 MIPS, 600 MIPS, high-speed, low-power, fixed point DSP, 130 nm, | | Summary | Full Text:PDF | |
|
|
|
|
|
|
|
Process Characterization and Optimization for a Novel Oxide-Free Insulated Gate Structure for InP MISFETs Having Silicon Interface Control Layer Hiroshi TAKAHASHI Masatsugu YAMADA Yong-Gui XIE Seiya KASAI Hideki HASEGAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2001/10/01
Vol. E84-C
No. 10
pp. 1344-1349
Type of Manuscript:
Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000)) Category: Hetero-FETs & Their Integrated Circuits Keyword: InP, MISFET, XPS, C-V, | | Summary | Full Text:PDF | |
|
|
|
|
|
|
|
A 1.2 V, 30 MIPS, 0.3 mA/MIPS and 200 MIPS, 0.58 mA/MIPS Digital Signal Processors Hiroshi TAKAHASHI Shintaro MIZUSHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C
No. 2
pp. 179-185
Type of Manuscript:
Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: high speed, super low power, MIPS, fixed point DSP, pocket implant, D flip-flop, VIA-2 ROM, 1.2 V, 200 MIPS, | | Summary | Full Text:PDF | |
|
|
|
|
|
|
|
|
|
|
|
A Circuit Library for Low Power and High Speed Digital Signal Processor Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuni OZAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C
No. 12
pp. 1717-1725
Type of Manuscript:
Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia) Category: Keyword: low power, high speed, low cost, GSM, PDC, NADC, digital signal processing, personal communication, 50 MIPS, CPU, | | Summary | Full Text:PDF | |
|
|
|
|
|
|
|
Fluorine Doping Levels in the Low-Pressure PCVD Process Ryoji SETAKA Hiroshi TAKAHASHI | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1984/06/25
Vol. E67-E
No. 6
pp. 333-334
Type of Manuscript:
LETTER Category: Optical and Quantum Electronics Keyword:
| | Summary | Full Text:PDF | |
|
|