Hiroshi RYU

Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis
Hidefumi KUROKAWA Hiroyuki IKEGAMI Motohide OTSUBO Kiyoshi ASAO Kazuhisa KIRIGAYA Katsuya MISU Satoshi TAKAHASHI Tetsuji KAWATSU Kouji NITTA Hiroshi RYU Kazutoshi WAKABAYASHI Minoru TOMOBE Wataru TAKAHASHI Akira MUKOUYAMA Takashi TAKENAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4  pp. 787-798
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
C-based design, behavioral synthesis, verification, design productivity, model abstraction, 
 Summary | Full Text:PDF(2.1MB)
Verification of Scalable-Delay-Insensitive Asynchronous Circuits
Atsushi YAMAZAKI Hiroshi RYU Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/03/25
Vol. E82-D  No. 3  pp. 701-703
Type of Manuscript:  LETTER
Category: Fault Tolerant Computing
Keyword: 
formal verification, asynchronous circuit, SDI model, bounded delay model, 
 Summary | Full Text:PDF(99.3KB)