Hiroshi NAKAHARA

A Layout-Oriented Routing Method for Low-Latency HPC Networks
Ryuta KAWANO Hiroshi NAKAHARA Ikki FUJIWARA Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   
Publication Date: 2017/12/01
Vol. E100-D  No. 12  pp. 2796-2807
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Interconnection networks
Keyword: 
high performance computing, network topology, interconnection networks, 
 Summary | Full Text:PDF(1.5MB)
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing
Ryuta KAWANO Hiroshi NAKAHARA Seiichi TADE Ikki FUJIWARA Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8  pp. 1798-1806
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
deadlock-free routing, high performance computing, time complexity, 
 Summary | Full Text:PDF(988.8KB)
Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface
Hiroshi NAKAHARA Tomoya OZAKI Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2871-2880
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
inductive coupling interconnect, interconnection network, network on chip, 
 Summary | Full Text:PDF(1.7MB)