IEICE Trans

Hiroo MASUDA

A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance Takashi SAITO Toshiki KANAMOTO Saiko KOBAYASHI Nobuhiko GOTO Takao SATO Hitoshi SUGIHARA Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/09/01 Vol. E93-A No. 9 pp. 1605-1611 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: LDMOS, macro model, gate-overlap capacitance, circuit simulation,
	Summary \| Full Text:PDF(1.6MB)

Impact of Self-Heating in Wire Interconnection on Timing Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 388-392 Type of Manuscript: BRIEF PAPER Category: Keyword: interconnect, delay variation, parasitic resistance, thermal, temperature, self-heat, SoC,
	Summary \| Full Text:PDF(221.9KB)

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3016-3023 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: low power, leakage, gate delay model, variation,
	Summary \| Full Text:PDF(1.1MB)

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 990-997 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: SSTA, output, transition time, gate delay model, process variation,
	Summary \| Full Text:PDF(2.6MB)

Comprehensive Matching Characterization of Analog CMOS Circuits Hiroo MASUDA Takeshi KIDA Shin-ichi OHKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 966-975 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: mismatch, small signal parameter, CMOS circuit, analog,
	Summary \| Full Text:PDF(2MB)

A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design Shin-ichi OHKAWA Hiroo MASUDA Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 1062-1070 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: LSI design, device variation, random curved surface, Gaussian, systematic part,
	Summary \| Full Text:PDF(2.3MB)

Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis Masakazu AOKI Shin-ichi OHKAWA Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 647-654 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: modeling transistor variations, within-die variation, statistical analysis for transistor parameters, SRAM cell sensitivity analysis, process window for SRAM cell operation,
	Summary \| Full Text:PDF(2.3MB)

Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 856-864 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: interconnect, worst-case delay, static timing analysis, process variation, capacitance extraction,
	Summary \| Full Text:PDF(509.1KB)

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills Atsushi KUROKAWA Akira KASEBE Toshiki KANAMOTO Yun YANG Zhangcai HUANG Yasuaki INOUE Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 847-855 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: dummy fill, capacitance extraction, capacitance formula, interconnect,
	Summary \| Full Text:PDF(507.9KB)

Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills Atsushi KUROKAWA Toshiki KANAMOTO Tetsuya IBE Akira KASEBE Wei Fong CHANG Tetsuro KAGE Yasuaki INOUE Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3471-3478 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: dummy metal, dummy fill, interconnect capacitance, CMP,
	Summary \| Full Text:PDF(466.8KB)

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance Atsushi KUROKAWA Masanori HASHIMOTO Akira KASEBE Zhangcai HUANG Yun YANG Yasuaki INOUE Ryosuke INAGAKI Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3453-3462 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: capacitance formula, capacitance calculation, capacitance extraction, interconnect capacitance,
	Summary \| Full Text:PDF(1.1MB)

A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills Atsushi KUROKAWA Toshiki KANAMOTO Akira KASEBE Yasuaki INOUE Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/11/01 Vol. E88-A No. 11 pp. 3180-3187 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: dummy fill, dummy metal, capacitance extraction, interconnect capacitance,
	Summary \| Full Text:PDF(489.6KB)

Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip Masakazu AOKI Shin-ichi OHKAWA Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/05/01 Vol. E88-C No. 5 pp. 788-795 Type of Manuscript: Special Section PAPER (Special Section on Microelectronic Test Structures) Category: Keyword: within-die parameter variation, random variation, systematic variation, correlation length, fitting function,
	Summary \| Full Text:PDF(2.1MB)

Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances Atsushi KUROKAWA Takashi SATO Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2933-2941 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: on-chip inductance, parasitic extraction, VLSI interconnects, inductance extraction,
	Summary \| Full Text:PDF(1.1MB)

100 nm-MOSFET Model for Circuit Simulation: Challenges and Solutions Mitiko MIURA-MATTAUSCH Hiroaki UENO Hans Juergen MATTAUSCH Keiichi MORIKAWA Satoshi ITOH Akiyoshi KOBAYASHI Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/06/01 Vol. E86-C No. 6 pp. 1009-1021 Type of Manuscript: INVITED PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems) Category: Keyword: MOSFET model, surface potential, device phenomena, RF applications,
	Summary \| Full Text:PDF(1.6MB)

Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects Atsushi KUROKAWA Kotaro HACHIYA Takashi SATO Kazuya TOKUMASU Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 pp. 841-845 Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: inductance, parasitic extraction, VLSI interconnect, geometric mean distance, skin effect,
	Summary \| Full Text:PDF(1018.5KB)

Delay Library Generation with High Efficiency and Accuracy on the Basis of RSM Hisako SATO Yuko ITO Hisaaki KUNITOMO Hiroyuki BABA Satoru ISOMURA Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/08/25 Vol. E83-C No. 8 pp. 1295-1302 Type of Manuscript: Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99)) Category: Simulation Methodology and Environment Keyword: delay library, RSM, circuit simulation,
	Summary \| Full Text:PDF(1.2MB)

A New Hierarchical RSM for TCAD-Based Device Design in 0.4µm CMOS Development Hisako SATO Katsumi TSUNENO Kimiko AOYAMA Takahide NAKAMURA Hisaaki KUNITOMO Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/02/25 Vol. E79-C No. 2 pp. 226-233 Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures) Category: Statistical Analysis Keyword: TCAD, RSM, CMOS design,
	Summary \| Full Text:PDF(742.5KB)

Modeling and Simulation on Degradation of Submicron NMOSFET Current Drive due to Velocity-Saturation Effects Katsumi TSUNENO Hisako SATO Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/02/25 Vol. E77-C No. 2 pp. 161-165 Type of Manuscript: Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93)) Category: Device Simulation Keyword: degradation of drain current, velocity-saturation, I_dso, lateral electric field,
	Summary \| Full Text:PDF(411.7KB)

Evaluation of Two-Dimensional Transient Enhanced Diffusion of Phosphorus during Shallow Junction Formation Hisako SATO Katsumi TSUNENO Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/02/25 Vol. E77-C No. 2 pp. 106-111 Type of Manuscript: Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93)) Category: Process Simulation Keyword: transient enhanced diffusion, two-dimension, phosphorus, silicon, shallow junction, furnace annealing,
	Summary \| Full Text:PDF(517.8KB)

Response Surface Methods for Submicron MOSFETs Characterization with Variable Transformation Technology Hiroo MASUDA Fumio OTSUKA Yukio AOKI Shoji SATO Shozo SHIMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/06/25 Vol. E74-C No. 6 pp. 1621-1633 Type of Manuscript: Special Section PAPER (Special Issue on Device and Process Simulation for Ultra Large Scale Integration) Category: Keyword:
	Summary \| Full Text:PDF(1MB)