Hiroo MASUDA


A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance
Takashi SAITO Toshiki KANAMOTO Saiko KOBAYASHI Nobuhiko GOTO Takao SATO Hitoshi SUGIHARA Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/09/01
Vol. E93-A  No. 9  pp. 1605-1611
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
LDMOSmacro modelgate-overlap capacitancecircuit simulation
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Impact of Self-Heating in Wire Interconnection on Timing
Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 388-392
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
interconnectdelay variationparasitic resistancethermaltemperatureself-heatSoC
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An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3016-3023
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
low powerleakagegate delay modelvariation
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Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 990-997
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
SSTAoutputtransition timegate delay modelprocess variation
 Summary | Full Text:PDF

Comprehensive Matching Characterization of Analog CMOS Circuits
Hiroo MASUDA Takeshi KIDA Shin-ichi OHKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 966-975
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
mismatchsmall signal parameterCMOS circuitanalog
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A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design
Shin-ichi OHKAWA Hiroo MASUDA Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1062-1070
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
LSI designdevice variationrandom curved surfaceGaussiansystematic part
 Summary | Full Text:PDF

Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis
Masakazu AOKI Shin-ichi OHKAWA Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 647-654
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
modeling transistor variationswithin-die variationstatistical analysis for transistor parametersSRAM cell sensitivity analysisprocess window for SRAM cell operation
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Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays
Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 856-864
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
interconnectworst-case delaystatic timing analysisprocess variationcapacitance extraction
 Summary | Full Text:PDF

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills
Atsushi KUROKAWA Akira KASEBE Toshiki KANAMOTO Yun YANG Zhangcai HUANG Yasuaki INOUE Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 847-855
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
dummy fillcapacitance extractioncapacitance formulainterconnect
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Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills
Atsushi KUROKAWA Toshiki KANAMOTO Tetsuya IBE Akira KASEBE Wei Fong CHANG  Tetsuro KAGE Yasuaki INOUE Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3471-3478
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
dummy metaldummy fillinterconnect capacitanceCMP
 Summary | Full Text:PDF

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance
Atsushi KUROKAWA Masanori HASHIMOTO Akira KASEBE Zhangcai HUANG Yun YANG Yasuaki INOUE Ryosuke INAGAKI Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3453-3462
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
capacitance formulacapacitance calculationcapacitance extractioninterconnect capacitance
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A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills
Atsushi KUROKAWA Toshiki KANAMOTO Akira KASEBE Yasuaki INOUE Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A  No. 11  pp. 3180-3187
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
dummy filldummy metalcapacitance extractioninterconnect capacitance
 Summary | Full Text:PDF

Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip
Masakazu AOKI Shin-ichi OHKAWA Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5  pp. 788-795
Type of Manuscript:  Special Section PAPER (Special Section on Microelectronic Test Structures)
Category: 
Keyword: 
within-die parameter variationrandom variationsystematic variationcorrelation lengthfitting function
 Summary | Full Text:PDF

Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
Atsushi KUROKAWA Takashi SATO Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2933-2941
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
on-chip inductanceparasitic extractionVLSI interconnectsinductance extraction
 Summary | Full Text:PDF

100 nm-MOSFET Model for Circuit Simulation: Challenges and Solutions
Mitiko MIURA-MATTAUSCH Hiroaki UENO Hans Juergen MATTAUSCH Keiichi MORIKAWA Satoshi ITOH Akiyoshi KOBAYASHI Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/06/01
Vol. E86-C  No. 6  pp. 1009-1021
Type of Manuscript:  INVITED PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems)
Category: 
Keyword: 
MOSFET modelsurface potentialdevice phenomenaRF applications
 Summary | Full Text:PDF

Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
Atsushi KUROKAWA Kotaro HACHIYA Takashi SATO Kazuya TOKUMASU Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4  pp. 841-845
Type of Manuscript:  Special Section LETTER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
inductanceparasitic extractionVLSI interconnectgeometric mean distanceskin effect
 Summary | Full Text:PDF

Delay Library Generation with High Efficiency and Accuracy on the Basis of RSM
Hisako SATO Yuko ITO Hisaaki KUNITOMO Hiroyuki BABA Satoru ISOMURA Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/08/25
Vol. E83-C  No. 8  pp. 1295-1302
Type of Manuscript:  Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Simulation Methodology and Environment
Keyword: 
delay libraryRSMcircuit simulation
 Summary | Full Text:PDF

A New Hierarchical RSM for TCAD-Based Device Design in 0.4µm CMOS Development
Hisako SATO Katsumi TSUNENO Kimiko AOYAMA Takahide NAKAMURA Hisaaki KUNITOMO Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2  pp. 226-233
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Statistical Analysis
Keyword: 
TCADRSMCMOS design
 Summary | Full Text:PDF

Modeling and Simulation on Degradation of Submicron NMOSFET Current Drive due to Velocity-Saturation Effects
Katsumi TSUNENO Hisako SATO Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/02/25
Vol. E77-C  No. 2  pp. 161-165
Type of Manuscript:  Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93))
Category: Device Simulation
Keyword: 
degradation of drain currentvelocity-saturationIdsolateral electric field
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Evaluation of Two-Dimensional Transient Enhanced Diffusion of Phosphorus during Shallow Junction Formation
Hisako SATO Katsumi TSUNENO Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/02/25
Vol. E77-C  No. 2  pp. 106-111
Type of Manuscript:  Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93))
Category: Process Simulation
Keyword: 
transient enhanced diffusiontwo-dimensionphosphorussiliconshallow junctionfurnace annealing
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Response Surface Methods for Submicron MOSFETs Characterization with Variable Transformation Technology
Hiroo MASUDA Fumio OTSUKA Yukio AOKI Shoji SATO Shozo SHIMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/06/25
Vol. E74-C  No. 6  pp. 1621-1633
Type of Manuscript:  Special Section PAPER (Special Issue on Device and Process Simulation for Ultra Large Scale Integration)
Category: 
Keyword: 
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