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Architecture of a Floating-Point Butterfly Execution Unit in a 400-MFLOPS Processor VLSI and Its Implementation Hironori YAMAUCHI Hiroshi MIYANAGA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C
No. 11
pp. 3852-3860
Type of Manuscript:
Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor) Category: Dedicated Processors Keyword:
| | Summary | Full Text:PDF(658.5KB) | |
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A 400 MFLOPS FFT Processor VLSI Architecture Hiroshi MIYANAGA Hironori YAMAUCHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C
No. 11
pp. 3845-3851
Type of Manuscript:
Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor) Category: Dedicated Processors Keyword:
| | Summary | Full Text:PDF(558.7KB) | |
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CMOS Radix-2 Signed-Digit Adder by Binary Code Representation Tadashi NAKANISHI Hironori YAMAUCHI Hiroshi YOSHIMURA | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/04/25
Vol. E69-E
No. 4
pp. 261-263
Type of Manuscript:
Special Section LETTER (Special Issue: Papers from 1986 National Convention IECE Japan) Category: Silicon Devices and Integrated Circuits Keyword:
| | Summary | Full Text:PDF(158.7KB) | |
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