Hironori AKAMATSU


0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier
Toshikazu SUZUKI Yoshinobu YAMAGAMI Ichiro HATANAKA Akinori SHIBAYAMA Hironori AKAMATSU Hiroyuki YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 630-638
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
SRAMlow-voltagewide-voltageSoC
 Summary | Full Text:PDF

A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs
Hironori AKAMATSU Toru IWATA Hiroyuki YAMAUCHI Hisakazu KOTANI Akira MATSUZAWA Hiro YAMAMOTO Takashi HIRATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1572-1577
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
multiple-threshold1-voltMT-CMOSdata storage circuitSRAMvirtual power lineintermittent connection
 Summary | Full Text:PDF

An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI'S
Hiroyuki YAMAUCHI Hironori AKAMATSU Tsutomu FUJITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 671-679
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
 Summary | Full Text:PDF

A Low Power Bus Architecture with Local and Global Charge-Recycling Bus Techniques for Battery-Operated Ultra-High Data Rate ULSI's
Hiroyuki YAMAUCHI Hironori AKAMATSU Tsutomu FUJITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4  pp. 394-403
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Digital Circuits
Keyword: 
charge-recyclinglow-powerbus-architecturesmall-swingultra-high-data-rate
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High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM
Toshikazu SUZUKI Toru IWATA Hironori AKAMATSU Akihiro SAWADA Toshiaki TSUJI Hiroyuki YAMAUCHI Takashi TANIGUCHI Tsutomu FUJITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1334-1342
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
DRAMcycle timebattery operatinghigh speed
 Summary | Full Text:PDF