IEICE Trans

Hiromi NOTANI

A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors Takahiro SHIMADA Hiromi NOTANI Yasunobu NAKASE Hiroshi MAKINO Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 571-577 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: low power consumption, I/O, parasitic bipolar transistor, forward bias, driver, level converter,
	Summary \| Full Text:PDF(740.3KB)

A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit Hiromi NOTANI Masayuki KOYAMA Ryuji MANO Hiroshi MAKINO Yoshio MATSUDA Osamu TOMISAWA Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 597-603 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Circuit Design Keyword: low power, standby current, backgate control, MT-CMOS,
	Summary \| Full Text:PDF(829.6KB)

Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller Akira YAMADA Yasuhiro NUNOMURA Hiroaki SUZUKI Hisakazu SATO Niichi ITOH Tetsuya KAGEMOTO Hironobu ITO Takashi KURAFUJI Nobuharu YOSHIOKA Jingo NAKANISHI Hiromi NOTANI Rei AKIYAMA Atsushi IWABU Tadao YAMANAKA Hidehiro TAKATA Takeshi SHIBAGAKI Takahiko ARAKAWA Hiroshi MAKINO Osamu TOMISAWA Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 635-642 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: microcontroller, high-speed, signal integrity, IR drop, design technique,
	Summary \| Full Text:PDF(1.9MB)

Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions Hideaki YAMANAKA Hirotaka SAITO Hirotoshi YAMADA Harufusa KONDOH Hiromi NOTANI Yoshio MATSUDA Kazuyoshi OSHIMA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1996/08/25 Vol. E79-B No. 8 pp. 1109-1120 Type of Manuscript: PAPER Category: Switching and Communication Processing Keyword: ATM switch architecture, hierarchical queueing, multicast functions, ATM access systems, ATM loop systems,
	Summary \| Full Text:PDF(1.3MB)

A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector Harufusa KONDOH Hiromi NOTANI Tsutomu YOSHIMURA Hiroshi SHIBATA Yoshio MATSUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/25 Vol. E78-C No. 4 pp. 381-388 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: Digital Circuits Keyword: PLL, PFD, VCO, CMOS, ATM,
	Summary \| Full Text:PDF(672.1KB)

A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs Harufusa KONDOH Hiromi NOTANI Hideaki YAMANAKA Keiichi HIGASHITANI Hirotaka SAITO Isamu HAYASHI Yoshio MATSUDA Kazuyoshi OSHIMA Masao NAKAYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1094-1101 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Improved Binary Digital Architectures Keyword: B-ISDN, ATM, switch, LSI, BiCMOS,
	Summary \| Full Text:PDF(854.7KB)

A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI Harufusa KONDOH Seiji KOZAKI Shinya MAKINO Hiromi NOTANI Fuminobu HIDANI Masao NAKAYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/03/25 Vol. E75-C No. 3 pp. 280-287 Type of Manuscript: Special Section PAPER (Special Issue on Analog LSI and Related Technology) Category: Keyword: PLL, pull-in range, oscillator, ISDN, primary rate interface,
	Summary \| Full Text:PDF(636.3KB)