IEICE Trans

Hirokazu MIYOSHI

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's Yasuo YAMAGUCHI Toshiyuki OASHI Takahisa EIMORI Toshiaki IWAMATSU Shouichi MITAMOTO Katsuhiro SUMA Takahiro TSURUDA Fukashi MORISHITA Masakazu HIROSE Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Yasuo INOUE Tadashi NISHIMURA Hirokazu MIYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 pp. 772-780 Type of Manuscript: INVITED PAPER (Special Issue on ULSI Memory Technology) Category: Dynamic RAMs Keyword: SOL, SIMOX, DRAM, low-voltage operation,
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Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories Hiroshi ONODA Yuichi KUNORI Kojiro YUZURIHA Shin-ichi KOBAYASHI Kiyohiko SAKAKIBARA Makoto OHI Atsushi FUKUMOTO Natsuo AJIKA Masahiro HATANAKA Hirokazu MIYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 pp. 1279-1286 Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: Non-volatile Memory Keyword: Fowler-Nordheim tunneling, virtual ground array, flash memory, NOR, asymmetrical source/drain structure,
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Deep Submicron Field Isolation with Buried Insulator between Polysilicon Electrodes (BIPS) Masahiro SHIMIZU Masahide INUISHI Katsuhiro TSUKAMOTO Hideaki ARIMA Hirokazu MIYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 pp. 1369-1376 Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: General Technology Keyword: isolation, parasitic field transistor, MOSFET,
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Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory Shin-ichi KOBAYASHI Hiroaki NAKAI Yuichi KUNORI Takeshi NAKAYAMA Yoshikazu MIYAWAKI Yasushi TERADA Hiroshi ONODA Natsuo AJIKA Masahiro HATANAKA Hirokazu MIYOSHI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/05/25 Vol. E77-C No. 5 pp. 784-790 Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
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Soft-Error Study of DRAMs with Retrograde Well Structure by New Evaluation Method Yoshikazu OHNO Hiroshi KIMURA Ken-ichiro SONODA Tadashi NISHIMURA Shin-ichi SATOH Hirokazu SAYAMA Shigenori HARA Mikio TAKAI Hirokazu MIYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/03/25 Vol. E77-C No. 3 pp. 399-405 Type of Manuscript: Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies) Category: Device Technology Keyword: soft-error, DRAM, microprobe, proton, mapping,
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