Hiroaki TAKAGI

Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade
Junichi AKITA Hiroaki TAKAGI Keisuke DOUMAE Akio KITAGAWA Masashi TODA Takeshi NAGASAKI Toshio KAWASHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1869-1875
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Image Sensor/Vision Chip
Keyword: 
line-of-sight (LoS), saccade, vision chip, column-parallel processing, 
 Summary | Full Text:PDF
Vision Chip Architecture for Detecting Line of Sight Including Saccade
Junichi AKITA Hiroaki TAKAGI Takeshi NAGASAKI Masashi TODA Toshio KAWASHIMA Akio KITAGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1605-1611
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
vision chip, line of sight, saccade, pixel parallel processing, automata, 
 Summary | Full Text:PDF
A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop
Yasutoshi AIBARA Eiki IMAIZUMI Hiroaki TAKAGISHI Tatsuji MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2  pp. 385-390
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
delay-locked loop (DLL), false lock, frequency range, duty cycle, digital camera, 
 Summary | Full Text:PDF