IEICE Trans

Hiroaki TAKADA

An Integrated Framework for Energy Optimization of Embedded Real-Time Applications Hideki TAKASE Gang ZENG Lovic GAUTHIER Hirotaka KAWASHIMA Noritoshi ATSUMI Tomohiro TATEMATSU Yoshitake KOBAYASHI Takenori KOSHIRO Tohru ISHIHARA Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2477-2487 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: energy optimization, compiler, profiler, real-time operating systems, embedded systems,
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Worst Case Response Time Analysis for Messages in Controller Area Network with Gateway Yong XIE Gang ZENG Yang CHEN Ryo KURACHI Hiroaki TAKADA Renfa LI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/07/01 Vol. E96-D No. 7 pp. 1467-1477 Type of Manuscript: PAPER Category: Software System Keyword: CAN, gateway, busy sequence, worst case response time, the minimum distance constraint,
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A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs Krzysztof JOZWIK Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 345-353 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: dynamic partial reconfiguration, hardware multitasking,
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Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems Hideki TAKASE Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/10/01 Vol. E94-A No. 10 pp. 1954-1964 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: scratch-pad memory, energy optimization, compiler, code allocation, multi-task systems,
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Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design Yuki ANDO Seiya SHIBATA Shinya HONDA Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2509-2516 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: system-level design, hardware sharing, design space exploration, MPSoC,
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Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems Tetsuo YOKOYAMA Gang ZENG Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/10/01 Vol. E93-D No. 10 pp. 2737-2746 Type of Manuscript: PAPER Category: Software System Keyword: battery-aware voltage scheduling, dynamic voltage scaling, low power, real-time systems,
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Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism Yuko HARA Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/02/01 Vol. E93-A No. 2 pp. 488-499 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: behavioral synthesis, function-level partitioning, integer programming problem,
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Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model Shan DING Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/07/01 Vol. E92-D No. 7 pp. 1412-1420 Type of Manuscript: PAPER Category: System Programs Keyword: I/O blocking, multi-frame task model, schedulability analysis, laxity, genetic algorithm,
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An Effective GA-Based Scheduling Algorithm for FlexRay Systems Shan DING Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/08/01 Vol. E91-D No. 8 pp. 2115-2123 Type of Manuscript: PAPER Category: System Programs Keyword: real-time systems, distributed embedded systems, FlexRay, genetic algorithm,
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Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis Yuko HARA Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA Katsuya ISHII
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2853-2862 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: behavioral synthesis, function-level partitioning, integer programming problem,
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Function Call Optimization for Efficient Behavioral Synthesis Yuko HARA Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/09/01 Vol. E90-A No. 9 pp. 2032-2036 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: behavioral synthesis, function calls, integer programming problem,
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An RTOS-Based Design and Validation Methodology for Embedded Systems Hiroyuki TOMIYAMA Shin-ichiro CHIKADA Shinya HONDA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/09/01 Vol. E88-D No. 9 pp. 2205-2208 Type of Manuscript: LETTER Category: System Programs Keyword: RTOS, cosimulation, embedded systems,
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RTOS-Centric Cosimulator for Embedded System Design Shinya HONDA Takayuki WAKABAYASHI Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3030-3035 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: RTOS, cosimulation, embedded systems,
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Memory Data Organization for Low-Energy Address Buses Hiroyuki TOMIYAMA Hiroaki TAKADA Nikil D. DUTT
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 606-612 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: compilers, embedded processors, memory data organization, low energy, bus encoding,
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