Hiroaki NAKAI


Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory
Shin-ichi KOBAYASHI Hiroaki NAKAI Yuichi KUNORI Takeshi NAKAYAMA Yoshikazu MIYAWAKI Yasushi TERADA Hiroshi ONODA Natsuo AJIKA Masahiro HATANAKA Hirokazu MIYOSHI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 784-790
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
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