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| Hiroaki KUNIEDA
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A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine
Hsuan-Chun LIAO Mochamad ASRI Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A
No. 6
pp. 1222-1235
Type of Manuscript:
Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category:
Keyword:
ASIP, image processing, | | | Summary | Full Text:PDF | |
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A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing
Hsuan-Chun LIAO Mochamad ASRI Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12
pp. 2373-2383
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
ASIP, image processing, | | | Summary | Full Text:PDF | |
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A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C
No. 6
pp. 956-963
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category:
Keyword:
capture range, CCO, CDR, clock and data recovery, false lock, jitter, NRZ, PFD, PLL, VCO, z-domain analysis, | | | Summary | Full Text:PDF | |
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FOREWORD
Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A
No. 10
pp. 1741-1741
Type of Manuscript:
FOREWORD
Category:
Keyword:
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A New Approach for Datapath Synthesis of Application Specific Instruction Processor
Kyung-Sik JANG Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/08/25
Vol. E80-A
No. 8
pp. 1478-1488
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
ASIP, datapath synthesis, architecture synthesis, | | | Summary | Full Text:PDF | |
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Memory Sharing Processor Array (MSPA) Architecture
Dongju LI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A
No. 12
pp. 2086-2096
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
processor array, data-path synthesis, systolic array, | | | Summary | Full Text:PDF | |
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Two-Dimensional Quadrilateral Recursive Digital Filters with Parallel Structure--Synthesis and Parallel Processing--
Tsuyoshi ISSHIKI Hiroaki KUNIEDA Mineo KANEKO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A
No. 3
pp. 352-361
Type of Manuscript:
Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
quadrilateral recursive filters, parallel processing, | | | Summary | Full Text:PDF | |
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Two Dimensional Space Partition Recursive Filtering Algorithm on Rectangular Processor Array
Yoshinori TAKEUCHI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/01/25
Vol. E74-A
No. 1
pp. 42-48
Type of Manuscript:
PAPER
Category: Digital Signal Processing
Keyword:
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