IEICE Trans

Hideyuki OZAKI

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros Akira YAMAZAKI Fukashi MORISHITA Naoya WATANABE Teruhiko AMANO Masaru HARAGUCHI Hideyuki NODA Atsushi HACHISUKA Katsumi DOSAKA Kazutami ARIMOTO Setsuo WAKE Hideyuki OZAKI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/10/01 Vol. E88-C No. 10 pp. 2020-2027 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: embedded memory, DRAM, voltage margin, low voltage, system on chip,
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A Low Power Embedded DRAM Macro for Battery-Operated LSIs Takeshi FUJINO Akira YAMAZAKI Yasuhiko TAITO Mitsuya KINOSHITA Fukashi MORISHITA Teruhiko AMANO Masaru HARAGUCHI Makoto HATAKENAKA Atsushi AMO Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2991-3000 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Power Optimization Keyword: embedded memory, DRAM, low power, system on chip,
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An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester Naoya WATANABE Fukashi MORISHITA Yasuhiko TAITO Akira YAMAZAKI Tetsushi TANIZAKI Katsumi DOSAKA Yoshikazu MOROOKA Futoshi IGAUE Katsuya FURUE Yoshihiro NAGURA Tatsunori KOMOIKE Toshinori MORIHARA Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 624-634 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: embedded DRAM, various DRAM macros, low voltage operation, short TAT, BIST,
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A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/09/01 Vol. E85-C No. 9 pp. 1697-1708 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: embedded DRAM, system on chip, 3-D graphics concurrent operation,
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Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs Fukashi MORISHITA Kazutami ARIMOTO Kazuyasu FUJISHIMA Hideyuki OZAKI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 253-259 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SOI, floating body, body control, high speed, low power,
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A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs Kiyohiro FURUTANI Tsukasa OOISHI Mikio ASAKURA Hideto HIDAKA Hideyuki OZAKI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/25 Vol. E80-C No. 4 pp. 582-589 Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Keyword: DRAM, test, redundancy,
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A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories Tsukasa OOISHI Yuichiro KOMIYA Kei HAMADE Mikio ASAKURA Kenichi YASUDA Kiyohiro FURUTANI Tetsuo KATO Hideto HIDAKA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/25 Vol. E79-C No. 7 pp. 986-996 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
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Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAM's Takeshi HAMAMOTO Yoshikazu MOROOKA Mikio ASAKURA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/25 Vol. E79-C No. 7 pp. 1003-1012 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
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A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pulse Width Modulation for AS-Memory Tadaaki YAMAUCHI Yoshikazu MOROOKA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/25 Vol. E79-C No. 7 pp. 934-941 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Interface Circuits Keyword:
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Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs Tadaaki YAMAUCHI Koji TANAKA Kiyohiro FURUTANI Yoshikazu MOROOKA Hiroshi MIYAMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 pp. 858-865 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: self-timing data-bus, timing delay, device fluctuation, amplifier, 64-Mb DRAMs,
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An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's Tsukasa OOISHI Yuichiro KOMIYA Kei HAMADE Mikio ASAKURA Kenichi YASUDA Kiyohiro FURUTANI Hideto HIDAKA Hiroshi MIYAMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/06/25 Vol. E78-C No. 6 pp. 719-727 Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995)) Category: Keyword:
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A Flexible Search Managing Circuitry for High-Density Dynamic CAMs Takeshi HAMAMOTO Tadato YAMAGATA Masaaki MIHARA Yasumitsu MURAI Toshifumi KOBAYASHI Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 pp. 1377-1384 Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: General Technology Keyword: content addressable memory, associative memory, dynamic memory, functional memory,
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An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's Yasuhiko TSUKIKAWA Takeshi KAJIMOTO Yasuhiko OKASAKA Yoshikazu MOROOKA Kiyohiro FURUTANI Hiroshi MIYAMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/05/25 Vol. E77-C No. 5 pp. 864-868 Type of Manuscript: Special Section LETTER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
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A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories Tadato YAMAGATA Masaaki MIHARA Takeshi HAMAMOTO Yasumitsu MURAI Toshifumi KOBAYASHI Michihiro YAMADA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 pp. 1657-1664 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: content addressable memory, associative memory, dynamic memory, redundancy,
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