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Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAM's Takeshi HAMAMOTO Yoshikazu MOROOKA Mikio ASAKURA Hideyuki OZAKI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C
No. 7
pp. 1003-1012
Type of Manuscript:
Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
| | Summary | Full Text:PDF(788.6KB) | |
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A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pulse Width Modulation for AS-Memory Tadaaki YAMAUCHI Yoshikazu MOROOKA Hideyuki OZAKI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C
No. 7
pp. 934-941
Type of Manuscript:
Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Interface Circuits Keyword:
| | Summary | Full Text:PDF(653.3KB) | |
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