Hideyuki NODA


A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications
Masanori HAYASHIKOSHI Hiroaki TANIZAKI Yasumitsu MURAI Takaharu TSUJI Kiyoshi KAWABATA Koji NII Hideyuki NODA Hiroyuki KONDO Yoshio MATSUDA Hideto HIDAKA 
Publication:   
Publication Date: 2019/04/01
Vol. E102-C  No. 4  pp. 287-295
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
nonvolatile memorymagnetic memorymemory architecture
 Summary | Full Text:PDF

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Takayuki GYOHTEN Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1409-1418
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
content addressable memoryCAMmatrix-processing architectureSIMDbit-serial and word-paralleltable-lookup codingDCTHuffman codingJPEG
 Summary | Full Text:PDF

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor
Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/08/01
Vol. E90-D  No. 8  pp. 1312-1315
Type of Manuscript:  LETTER
Category: Image Processing and Video Processing
Keyword: 
DCTfast DCTmatrix-processing engineSIMDbit-serial and word-parallel
 Summary | Full Text:PDF

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
Fukashi MORISHITA Hideyuki NODA Isamu HAYASHI Takayuki GYOHTEN Mako OKAMOTO Takashi IPPOSHI Shigeto MAEGAWA Katsumi DOSAKA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 765-771
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
SOIcapacitorlessDRAMlow powerdata retention
 Summary | Full Text:PDF

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer
Takeshi KUMAKI Yasuto KURODA Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 334-345
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
content addressable memoryCAMHuffman codingparallel processingpipelinecode word table
 Summary | Full Text:PDF

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC
Hideyuki NODA Katsumi DOSAKA Hans Jurgen MATTAUSCH Tetsushi KOIDE Fukashi MORISHITA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1612-1619
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
soft errorECCTCAMembeddedDRAM
 Summary | Full Text:PDF

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design
Takayuki GYOHTEN Fukashi MORISHITA Isamu HAYASHI Mako OKAMOTO Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1519-1525
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
PVT variationtemperature detectionseries regulator
 Summary | Full Text:PDF

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros
Akira YAMAZAKI Fukashi MORISHITA Naoya WATANABE Teruhiko AMANO Masaru HARAGUCHI Hideyuki NODA Atsushi HACHISUKA Katsumi DOSAKA Kazutami ARIMOTO Setsuo WAKE Hideyuki OZAKI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/10/01
Vol. E88-C  No. 10  pp. 2020-2027
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
embedded memoryDRAMvoltage marginlow voltagesystem on chip
 Summary | Full Text:PDF

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features
Kazunari INOUE Hideyuki NODA Kazutami ARIMOTO Hans Jurgen MATTAUSCH Tetsushi KOIDE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6  pp. 1332-1342
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
CAMTCAMsignature-matchingnetwork security
 Summary | Full Text:PDF

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh
Hideyuki NODA Kazunari INOUE Hans Jurgen MATTAUSCH Tetsushi KOIDE Katsumi DOSAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Kenji ANAMI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 622-629
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
CMOSTernary CAMnetworkrefresh
 Summary | Full Text:PDF

A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/09/01
Vol. E85-C  No. 9  pp. 1697-1708
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
embedded DRAMsystem on chip3-D graphics concurrent operation
 Summary | Full Text:PDF