IEICE Trans

Hideyuki ICHIHARA

Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines Hideyuki ICHIHARA Motoi FUKUDA Tsuyoshi IWAGAKI Tomoo INOUE
Publication: Publication Date: 2020/12/01 Vol. E103-A No. 12 pp. 1464-1471 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: approximate computing, soft error, Markov model, Hamming distance, motion detection,
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Hybrid Test Application in Partial Skewed-Load Scan Design Yuki YOSHIKAWA Tomomi NUWA Hideyuki ICHIHARA Tomoo INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2571-2578 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: delay testing, design-for-testability, skewed-load test application, broad-side test application, partial skewed-load scan design, hybrid test application,
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A Practical Threshold Test Generation for Error Tolerant Application Hideyuki ICHIHARA Kenta SUTOH Yuki YOSHIKAWA Tomoo INOUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/10/01 Vol. E93-D No. 10 pp. 2776-2782 Type of Manuscript: PAPER Category: Information Network Keyword: acceptable fault, test generation model, error significance, threshold testing and error tolerance,
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Design and Optimization of Transparency-Based TAM for SoC Test Tomokazu YONEDA Akiko SHUTO Hideyuki ICHIHARA Tomoo INOUE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/06/01 Vol. E93-D No. 6 pp. 1549-1559 Type of Manuscript: PAPER Category: Information Network Keyword: SoC test, design for testability, TAM design, transparency, ILP,
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An Architecture of Embedded Decompressor with Reconfigurability for Test Compression Hideyuki ICHIHARA Tomoyuki SAIKI Tomoo INOUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 713-719 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Test Compression Keyword: test compression, ATE, reconfigurability, variable-length coding, test application,
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A Self-Test of Dynamically Reconfigurable Processors with Test Frames Tomoo INOUE Takashi FUJII Hideyuki ICHIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 756-762 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: High-Level Testing Keyword: dynamically reconfigurable processors, self-test, optimal contexts, test application time, test frames,
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A Variable-Length Coding Adjustable for Compressed Test Application Hideyuki ICHIHARA Toshihiro OHARA Michihiro SHINTANI Tomoo INOUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/08/01 Vol. E90-D No. 8 pp. 1235-1242 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test compression, variable-length coding, test application time, ATE, Huffman code, and test environment,
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Huffman-Based Test Response Coding Hideyuki ICHIHARA Michihiro SHINTANI Tomoo INOUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/01/01 Vol. E88-D No. 1 pp. 158-161 Type of Manuscript: LETTER Category: Dependable Computing Keyword: Huffman code, test compression, test response, test application time, ATE,
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A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG Hideyuki ICHIHARA Tomoo INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3072-3078 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: test generation, acyclic sequential circuits, stuck-at fault, partial scan, multiple fault,
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Test Generation for Test Compression Based on Statistical Coding Hideyuki ICHIHARA Atsuhiro OGAWA Tomoo INOUE Akio TAMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1466-1473 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test Generation and Modification Keyword: VLSI test, test compression, statistical code, test generation, automatic test equipment,
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On Processing Order for Obtaining Implication Relations in Static Learning Hideyuki ICHIHARA Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/10/25 Vol. E83-D No. 10 pp. 1908-1911 Type of Manuscript: LETTER Category: Fault Tolerance Keyword: test generation, implication, static learning,
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Logic Optimization: Redundancy Addition and Removal Using Implication Relations Hideyuki ICHIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 724-730 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Logic Simulation and Logic Optimization Keyword: logic optimization, implication, redundancy identification,
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