IEICE Trans

Hidetoshi ONODERA

Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region Shoya SONODA Jun SHIOMI Hidetoshi ONODERA
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1566-1576 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: minimum energy point tracking (MEPT), dynamic voltage and frequency scaling (DVFS), adaptive body biasing (ABB),
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Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration Hongjie XU Jun SHIOMI Hidetoshi ONODERA
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1488-1498 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: convolutional neural networks, machine learning, low power circuit design, VLSI, parallel processing,
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A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits Ryosuke MATSUO Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA Akihiko SHINYA Masaya NOTOMI
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1546-1554 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: binary decision diagram, logic circuit, optical circuit,
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A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation Kentaro NAGAI Jun SHIOMI Hidetoshi ONODERA
Publication: Publication Date: 2021/10/01 Vol. E104-C No. 10 pp. 617-624 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: body bias generator, minimum energy point tracking (MEPT), adaptive body bias (ABB), analog-assisted digital,
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Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm² Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS Akira TSUCHIYA Akitaka HIRATSUKA Kenji TANAKA Hiroyuki FUKUYAMA Naoki MIURA Hideyuki NOSAKA Hidetoshi ONODERA
Publication: Publication Date: 2020/10/01 Vol. E103-C No. 10 pp. 489-496 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Integrated Electronics Keyword: optical communication, transimpedance amplifier, inductive peaking, on-chip inductor,
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On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing Hongjie XU Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 pp. 1741-1750 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: standard-cell memory, SRAM, near-threshold computing, cache memory, system-on-chip,
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Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits Ryosuke MATSUO Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA Akihiko SHINYA Masaya NOTOMI
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 pp. 1751-1759 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: binary decision diagram, logic circuit, optical circuit,
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A Design Method of a Cell-Based Amplifier for Body Bias Generation Takuya KOYANAGI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 565-572 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: body bias generator, cell-based-design, analog-assisted digital, amplifier, low power,
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Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity Akira TSUCHIYA Akitaka HIRATSUKA Toshiyuki INOUE Keiji KISHINE Hidetoshi ONODERA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 573-579 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: power integrity, signal integrity, multi-layered inductor,
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Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis Shinichi NISHIZAWA Hidetoshi ONODERA
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2222-2230 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: D-Flip-Flop, variation aware design, regression analysis,
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A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing Shu HOKIMOTO Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2776-2784 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: minimum energy point tracking (MEPT), dynamic voltage and frequency scaling (DVFS), adaptive body biasing (ABB),
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A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2764-2775 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: minimum energy point tracking (MEPT), dynamic voltage and frequency scaling (DVFS), adaptive body biasing (ABB), standard-cell based memory (SCM),
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Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Tatsuya KAMAKARI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2463-2472 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: latch, low voltage design, stability modeling,
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Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1455-1466 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: near-threshold computing, statistical static timing analysis (SSTA),
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A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage Norihiro KAMAE Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/06/01 Vol. E98-C No. 6 pp. 504-511 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: body bias generator, dynamic voltage frequency scaling, low supply voltage, analog-assisted digital, switched-capacitor circuits,
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Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/04/01 Vol. E98-C No. 4 pp. 298-303 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology) Category: Keyword: Neutron-induced Soft Error, Multiple Cell Upset (MCU), cell distance, well-contact density, Flip-Flop,
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Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Hajime SHIMADA Kazutoshi KOBAYASHI Hiroyuki KANBARA Hiroyuki OCHI Takashi IMAGAWA Kazutoshi WAKABAYASHI Masanori HASHIMOTO Takao ONOYE Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2518-2529 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: reconfigurable architecture, soft error, radiation test, behavioral synthesis, state machine,
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Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure SinNyoung KIM Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 pp. 325-331 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: radiation-hardened phase-locked loop (RH-PLL), PLL, radiation-hardened-by-design (RHBD), dual modular redundancy (DMR),
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Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop SinNyoung KIM Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/03/01 Vol. E97-A No. 3 pp. 768-776 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: radiation-hardened phase-locked loop (RH-PLL), soft error, clock-perturbation model,
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A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation Norihiro KAMAE Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/03/01 Vol. E97-A No. 3 pp. 734-740 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: body bias generator, dynamic voltage frequency scaling, analog-assisted digital, low supply voltage,
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Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation Shinichi NISHIZAWA Tohru ISHIHARA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2499-2507 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: standard cell design, low power circuit design, near threshold operation, PN ratio optimization,
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On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation A.K.M. Mahfuzul ISLAM Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 pp. 1971-1979 Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing) Category: Keyword: process shift, process spread, monitor structure, post-silicon analysis, delay test, adaptive test,
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A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect Kuiyuan ZHANG Jun FURUTA Ryosuke YAMAMOTO Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 511-517 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: DMR, soft error, MCU, device simulation,
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Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System Takeshi KUBOKI Yusuke OHTOMO Akira TSUCHIYA Keiji KISHINE Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/02/01 Vol. E95-A No. 2 pp. 479-486 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: interwoven inductor, LD driver, optical communication,
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Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures Chikara HAMANAKA Ryosuke YAMAMOTO Jun FURUTA Kanto KUBOTA Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2669-2675 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: soft error, hardened design, variability, test structure, shift register,
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An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 340-346 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: TMR, built-in soft error, SEU, SET,
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Statistical Gate Delay Model for Multiple Input Switching Takayuki FUKUOKA Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3070-3078 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: statistical static timing analysis, multiple input switching, statistical maximum operation,
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Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration Hirofumi SHINOHARA Koji NII Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 pp. 1488-1500 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: SRAM, memory cell, static noise margin, SNM, variability,
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Timing Analysis Considering Temporal Supply Voltage Fluctuation Masanori HASHIMOTO Junji YAMAGUCHI Takashi SATO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 655-660 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Verification and Timing Analysis Keyword: timing analysis, dynamic power supply noise,
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Manufacturability-Aware Design of Standard Cells Hirokazu MUTA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2682-2690 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: manufacturability, variability, DFM, ACLV, standard cell, OPC, RET,
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Timing Analysis Considering Spatial Power/Ground Level Variation Masanori HASHIMOTO Junji YAMAGUCHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2661-2668 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: timing analysis, power supply noise, gate delay model, power/ground level variation,
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A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations Kazutoshi KOBAYASHI Kazuya KATSUKI Manabu KOTANI Yuuri SUGIHARA Yohei KUME Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1919-1926 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Low-Power and High-Performance VLSI Circuit Technology Keyword: variation-aware, reconfigurable device, FPGA, yield, DFM,
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Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver Takeshi KUBOKI Akira TSUCHIYA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1274-1281 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: on-chip signaling, current-mode logic,
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Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1267-1273 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: on-chip transmission-line, termination,
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A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations Kazuya KATSUKI Manabu KOTANI Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 699-707 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: within-die variation, reconfigurable device, FPGA, LUT (look-up table), yield,
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FOREWORD Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3377-3377 Type of Manuscript: FOREWORD Category: Keyword:
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Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design Toshiki KANAMOTO Tatsuhiko IKEDA Akira TSUCHIYA Hidetoshi ONODERA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3560-3568 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: substrate, interconnect, resistance, inductance, SoC,
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Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3585-3593 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: parameter extraction, transmission-line, frequency dependence,
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A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era Kazutoshi KOBAYASHI Akihiko HIGUCHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/06/01 Vol. E89-C No. 6 pp. 838-843 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: sleep transistor, decoupling capacitor, MTCMOS, low power,
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Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect Yoichi YUYAMA Akira TSUCHIYA Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 327-333 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Interface and Interconnect Techniques Keyword: alternate self shielding, on-chip global interconnect, critical transition and bus encoding,
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Variability: Modeling and Its Impact on Design Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 342-348 Type of Manuscript: INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Keyword: variability, within-die variability, die-to-die variability, statistical design,
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Effects of On-Chip Inductance on Power Distribution Grid Atsushi MURAMATSU Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3564-3572 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: power distribution network, on-chip inductance, power supply noise, decoupling capacitance,
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Successive Pad Assignment for Minimizing Supply Voltage Drop Takashi SATO Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3429-3436 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Power/Ground Network Keyword: successive pad assignment (SPA), incremental matrix inversion (IMI), voltage drop, power distribution network,
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Statistical Analysis of Clock Skew Variation in H-Tree Structure Masanori HASHIMOTO Tomonori YAMAMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3375-3381 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: clock skew, manufacturing variability, environmental variability, transition time constraint, statistical analysis, clock distribution,
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A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era Kazutoshi KOBAYASHI Masao ARAMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 552-558 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Digital Keyword: parallel processing, VLIW, SMT, low power, nanometer, leakage power,
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Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 885-891 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: global interconnect, high-speed signaling, performance limitation,
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A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL Takahito MIYAZAKI Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/03/01 Vol. E88-C No. 3 pp. 437-444 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: clock generation PLL, LC oscillator, ring oscillator, performance prediction, jitter, power consumption, chip area,
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Crosstalk Noise Optimization by Post-Layout Transistor Sizing Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3251-3257 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: crosstalk noise, capacitive coupling noise, transistor sizing, gate sizing, post-layout optimization,
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Design Optimization Methodology for On-Chip Spiral Inductors Kenichi OKADA Hiroaki HOSHINO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/06/01 Vol. E87-C No. 6 pp. 933-941 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Keyword: spiral inductor, response surface method, optimization, quality factor,
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Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers Akihiko HIGUCHI Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/04/01 Vol. E87-A No. 4 pp. 823-829 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: embedded processor, power estimation, instruction-level,
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An Efficient Motion Estimation Algorithm Using a Gyro Sensor Kazutoshi KOBAYASHI Ryuta NAKANISHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/03/01 Vol. E87-A No. 3 pp. 530-538 Type of Manuscript: Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing) Category: Video/Image Coding Keyword: motion estimation, gyro sensor, MPEG-4,
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A Comprehensive Simulation and Test Environment for Prototype VLSI Verification Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 630-636 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Verification Keyword: simulation, test, VLSI, tester, verification,
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Experimental Study on Cell-Base High-Performance Datapath Design Masanori HASHIMOTO Yoshiteru HAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3204-3207 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: IP Design Keyword: datapath design, bit-slice layout, transistor sizing, cell-base design,
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Crosstalk Noise Estimation for Generic RC Trees Masanori HASHIMOTO Masao TAKAHASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2965-2973 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: crosstalk noise, capacitive coupling, noise estimation, signal integrity,
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Representative Frequency for Interconnect R(f)L(f)C Extraction Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2942-2951 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: interconnect, extraction, frequency-dependent,
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Statistical Gate-Delay Modeling with Intra-Gate Variability Kenichi OKADA Kento YAMAOKA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2914-2922 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: intra-chip variability, statistical timing analysis, intra-gate variability, manufacturing fluctuation,
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Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence Kenichi OKADA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 pp. 746-751 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: intra-chip variability, statistical timing analysis, manufacturing fluctuation,
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Increase in Delay Uncertainty by Performance Optimization Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2799-2802 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Analysis Keyword: performance optimization, delay increase, statistical timing analysis, delay uncertainty, transistor sizing,
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Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2769-2777 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: transistor sizing, low power design, cell-base design, post-layout optimization, gate sizing,
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A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance Takeo YASUDA Hiroaki FUJITA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2793-2801 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Analog Design Keyword: PLL, phase adjust, variable delay, lock-up,
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FOREWORD Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2613-2613 Type of Manuscript: FOREWORD Category: Keyword:
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A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis' Distance Tomohiro FUJITA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/03/01 Vol. E84-A No. 3 pp. 727-734 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: analog LSI, yield optimization, hierarchical design, constraint generation, Mahalanobis' distance,
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A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones Kazutoshi KOBAYASHI Makoto EGUCHI Takuya IWAHASHI Takehide SHIBAYAMA Xiang LI Kosuke TAKAI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 193-201 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: VLSI, DSP, MSHVQ, videophone, video compression,
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Statistical Modeling of Device Characteristics with Systematic Variability Kenichi OKADA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/02/01 Vol. E84-A No. 2 pp. 529-536 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques Supporting the System LSI Era) Category: Keyword: MOSFET, variability, systematic, stochastic,
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A Method for Linking Process-Level Variability to System Performances Tomohiro FUJITA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2592-2599 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation Keyword: analog VLSI circuit, statistical analysis, hierarchical analysis, response surface model, intermediate mode,
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Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2400-2408 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: VLSI, functional memory, DRAM, parallel processor, block matching,
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A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2558-2568 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Performance Optimization Keyword: statistical static timing analysis, static timing analysis, gate resizing, transistor sizing, performance optimization,
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Layout Dependent Matching Analysis of CMOS Circuits Kenichi OKADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 348-355 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: CMOS, matching, micro-loading-effect, fluctuation,
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A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization Kazutoshi KOBAYASHI Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 pp. 215-222 Type of Manuscript: Special Section PAPER (Special Section on VLSI for Digital Signal Processing) Category: Keyword: vector quantization, functional memory, parallel processor, low-rate image compression, noise robustness, MSHVQ,
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A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits Masanori HASHIMOTO Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/01/25 Vol. E82-A No. 1 pp. 159-166 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: input reordering, transistor reordering, power estimation,
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An LSI for Low Bit-Rate Image Compression Using Vector Quantization Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 pp. 718-724 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: parallel processor, memory-based, vector quantization, low bit-rate image compression, low power, SIMD,
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Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load Akio HIRATA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/03/25 Vol. E81-A No. 3 pp. 462-469 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems) Category: Keyword: short-circuit power dissipation, short-circuit current, resistive-capacitive load, CRC π load, output waveform, gate delay,
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A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ Kazutoshi KOBAYASHI Masayoshi KINOSHITA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 970-975 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Multi Processors Keyword: parallel processor, memory-base, vector quantization, low bit-rate image compression, SIMD,
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A Current Mode Cyclic A/D Converter with Submicron Processes Masaki KONDO Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/02/25 Vol. E80-A No. 2 pp. 360-364 Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques for System-on-Chip Integration) Category: Keyword: A/D, A/D converter, current mode, ratio-independent, RGC,
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Estimation of short-Circuit Power Dissipation for Static CMOS Gates Akio HIRATA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 pp. 304-311 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: short-circuit power dissipation, short-circit current, simulation of power dissipation, low power disign, power estimation,
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Model-Adaptable Parameter Extraction System for MOSFET Models Masaki KONDO Takashi MORIE Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/05/25 Vol. E78-A No. 5 pp. 569-572 Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Fall Conference) Category: Keyword: parameter extraction system, initial value estimation, MOSFET characterization,
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Compaction with Shape Optimization and Its Application to Layout Recycling Kazuhisa OKADA Hidetoshi ONODERA Keikichi TAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/02/25 Vol. E78-A No. 2 pp. 169-176 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Computer Aided Design) Category: Keyword: analog layout, compaction, shape optimization, layout recycling,
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Development of Module Generators from Extracted Design Procedures--Application to Analog Device Generation-- Takashi MORIE Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/02/25 Vol. E78-A No. 2 pp. 160-168 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Computer Aided Design) Category: Keyword: device layout, module generation, analog LSI, store and re-use, design procedure,
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Experiments with Power Optimization in Gate Sizing Guangqiu CHEN Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/11/25 Vol. E77-A No. 11 pp. 1913-1916 Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference) Category: Keyword: low power design, power dissipation, gate sizing, area–power–delay tradeoff,
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A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture Kazutoshi KOBAYASHI Keikichi TAMARU Hiroto YASUURA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1151-1158 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Memory-Based Parallel Processor Architectures Keyword: parallel processor, memory-based simple structure, logical and arithmetic operations,
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Hardware Architecture for Kohonen Network Hidetoshi ONODERA Kiyoshi TAKESHITA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1159-1166 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Neural Networks and Chips Keyword: neural network, Kohonen network, massively parallel computation, content addressable memory,
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Module Generation of a CMOS Op Amp Using a Non-linear Optimization Method Hidetoshi ONODERA Hiroyuki KANBARA Keikichi TAMARU
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1988/10/25 Vol. E71-E No. 10 pp. 947-949 Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1988 Autumn Convention IEICE) Category: Integrated Circuit Keyword:
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