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Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age Takashi KONO Yasuhiko TAITO Hideto HIDAKA | Publication:
Publication Date: 2020/04/01
Vol. E103-C
No. 4
pp. 132-143
Type of Manuscript:
INVITED PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Integrated Electronics Keyword: edge computing, embedded system, embedded flash memory, IoT, AI, | | Summary | Full Text:PDF(3.3MB) | |
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A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's Tsukasa OOISHI Mikio ASAKURA Shigeki TOMISHIMA Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C
No. 5
pp. 762-770
Type of Manuscript:
Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
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A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 508-515
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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A Dual-Mode Sensing Scheme of Capacitor-Coupled EEPROM Cell Masanori HAYASHIKOSHI Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 467-471
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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Cell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM's Mikio ASAKURA Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 495-500
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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A Divided/Pausing Bitline Sensing Scheme (DIPS) for ULSI DRAM Core Hideto HIDAKA Yoshio MATSUDA Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E
No. 11
pp. 1852-1854
Type of Manuscript:
Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE) Category: Integrated Circuits Keyword:
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A Passive TE/TM Mode Splitting Device by the Ion-Exchanged LiNbO3 Waveguide Yoichi FUJII Hideto HIDAKA | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1985/02/25
Vol. E68-E
No. 2
pp. 111-112
Type of Manuscript:
LETTER Category: Optical and Quantum Electronics Keyword:
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