Hideo TAMAMOTO


Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design
Katsuya FUJIWARA Hideo FUJIWARA Hideo TAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7  pp. 1430-1439
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designshift register equivalentssecurityscan-based side-channel attack
 Summary | Full Text:PDF(599.1KB)

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies
Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/04/01
Vol. E88-D  No. 4  pp. 703-710
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
fault diagnosisIDDQtransistor leakage fault modelmultiple power supplycircuit partitioning
 Summary | Full Text:PDF(487.3KB)

Improving Random Pattern Testability with Partial Circuit Duplication Approach
Hiroshi YOKOYAMA Xiaoqing WEN Hideo TAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 654-659
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
Keyword: 
partial circuit duplicationrandom testingdesign for testabilitybuilt-in self-test
 Summary | Full Text:PDF(579.7KB)

Transistor Leakage Fault Diagnosis for CMOS Circuits
Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 697-705
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
fault diagnosistransistor leakage faultIDDQprimary outputfault simulationdiagnostic test generation
 Summary | Full Text:PDF(868.3KB)

Transistor Leakage Fault Diagnosis with IDDQ and Logic Information
Wen XIAOQING Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/04/25
Vol. E81-D  No. 4  pp. 372-381
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault diagnosistransistor leakage faultIDDQ testingfault simulationdiagnostic vector generation
 Summary | Full Text:PDF(985.7KB)

Testing of k-FR Circuits under Highly Observable Condition
Xiaoqing WEN Hideo TAMAMOTO Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 830-838
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
testable designfault testinghighly observable conditioncircuit conversion
 Summary | Full Text:PDF(754.1KB)

Efficient Guided-Probe Fault Location Method for Sequential Circuits
Xiaoging WEN Kozo KINOSHITA Hideo TAMAMOTO Hiroshi YOKOYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/02/25
Vol. E78-D  No. 2  pp. 122-129
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
guided-probe fault locationselection of lines to probesequential circuitVLSI diagnosis
 Summary | Full Text:PDF(713KB)

Analysis of Fault Detection Probability of Random Access Memories in Applying Random Patterns
Hideo TAMAMOTO Tatsumi OHTAKA Yuichi NARITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1991/11/25
Vol. E74-D  No. 11  pp. 3910-3920
Type of Manuscript:  LETTER
Category: Fault Tolerant Computing
Keyword: 
 Summary | Full Text:PDF(401.7KB)