IEICE Trans

Hideo TAMAMOTO

Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design Katsuya FUJIWARA Hideo FUJIWARA Hideo TAMAMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/07/01 Vol. E94-D No. 7 pp. 1430-1439 Type of Manuscript: PAPER Category: Dependable Computing Keyword: design-for-testability, scan design, shift register equivalents, security, scan-based side-channel attack,
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On Design for I_DDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/04/01 Vol. E88-D No. 4 pp. 703-710 Type of Manuscript: PAPER Category: Computer Components Keyword: fault diagnosis, I_DDQ, transistor leakage fault model, multiple power supply, circuit partitioning,
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Improving Random Pattern Testability with Partial Circuit Duplication Approach Hiroshi YOKOYAMA Xiaoqing WEN Hideo TAMAMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 654-659 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Design for Testability Keyword: partial circuit duplication, random testing, design for testability, built-in self-test,
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Transistor Leakage Fault Diagnosis for CMOS Circuits Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 697-705 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Fault Diagnosis Keyword: fault diagnosis, transistor leakage fault, I_DDQ, primary output, fault simulation, diagnostic test generation,
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Transistor Leakage Fault Diagnosis with I_DDQ and Logic Information Wen XIAOQING Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/04/25 Vol. E81-D No. 4 pp. 372-381 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: fault diagnosis, transistor leakage fault, I_DDQ testing, fault simulation, diagnostic vector generation,
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Testing of k-FR Circuits under Highly Observable Condition Xiaoqing WEN Hideo TAMAMOTO Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-D No. 7 pp. 830-838 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: testable design, fault testing, highly observable condition, circuit conversion,
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Efficient Guided-Probe Fault Location Method for Sequential Circuits Xiaoging WEN Kozo KINOSHITA Hideo TAMAMOTO Hiroshi YOKOYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/02/25 Vol. E78-D No. 2 pp. 122-129 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: guided-probe fault location, selection of lines to probe, sequential circuit, VLSI diagnosis,
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Analysis of Fault Detection Probability of Random Access Memories in Applying Random Patterns Hideo TAMAMOTO Tatsumi OHTAKA Yuichi NARITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1991/11/25 Vol. E74-D No. 11 pp. 3910-3920 Type of Manuscript: LETTER Category: Fault Tolerant Computing Keyword:
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