Hideo ITO


Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/10/01
Vol. E97-D  No. 10  pp. 2719-2729
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small-delay defectsfault coveragesegmented scancontrol pointobservation point
 Summary | Full Text:PDF

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/03/01
Vol. E97-D  No. 3  pp. 533-540
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small-delay defectstest compactiontest application timetest data volumeon-chip delay measurement
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Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
Kazuteru NAMBA Nobuhide TAKASHINA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1613-1623
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Test and Verification
Keyword: 
small delay defectsdelay measurementDVMC (delay value measurement circuit)FPGA (field programmable gate array)global routing resource
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Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/05/01
Vol. E96-D  No. 5  pp. 1219-1222
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
small delay faultstest coverageflip-flopclock pulse
 Summary | Full Text:PDF

FOREWORD
Hideo ITOZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/03/01
Vol. E96-C  No. 3  pp. 297-297
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF

Construction of BILBO FF with Soft-Error-Tolerant Capability
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/05/01
Vol. E94-D  No. 5  pp. 1045-1050
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
soft-error-toleranceDFT (design for test)BISER (built-in soft-error resilience)BILBO (built-in logic block observer)reconfigurable C-element
 Summary | Full Text:PDF

Single-Event-Upset Tolerant RS Flip-Flop with Small Area
Kazuteru NAMBA Kengo NAKASHIMA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/12/01
Vol. E93-D  No. 12  pp. 3407-3409
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
soft errorsingle-event-upset (SEU) tolerancereset-set flip-flop (RS-FF)interlocking feedback loop
 Summary | Full Text:PDF

Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9  pp. 2295-2303
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
two-rail logic circuitpath delay faulttestabilityfunctional sensitizabilityover-testing
 Summary | Full Text:PDF

Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability
Shuangyu RUAN Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/08/01
Vol. E92-D  No. 8  pp. 1534-1541
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
soft errorwide pulseflip-flopC-elementdelay element
 Summary | Full Text:PDF

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/03/01
Vol. E92-D  No. 3  pp. 433-442
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
dual circuitsmaster and slave scan pathsdelay fault testingconcurrent error detectionDFT
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Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2  pp. 269-282
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test compressionstatistical codingrun-length codingdelay fault testingtwo-pattern testingscan testing
 Summary | Full Text:PDF

Design for Delay Fault Testability of 2-Rail Logic Circuits
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2  pp. 336-341
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
2-rail logic circuitsdesign for testabilitydelay fault testingscan designset-reset operation
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A Checkpointing Method with Small Checkpoint Latency
Masato KITAKAMI Bochuan CAI Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 857-861
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
dependabilitycheckpointingcheckpoint overheadcheckpoint latencysubcheckpoint
 Summary | Full Text:PDF

Low-Cost IP Core Test Using Tri-Template-Based Codes
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 288-295
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design for testabilityIP core testingtest cost reductiontest data compression
 Summary | Full Text:PDF

Redundant Design for Wallace Multiplier
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/09/01
Vol. E89-D  No. 9  pp. 2512-2524
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
Wallace multiplierbit-slice reconfiguration redundant designdefect-toleranceyield
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Proposal of Testable Multi-Context FPGA Architecture
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/05/01
Vol. E89-D  No. 5  pp. 1687-1693
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
multi-context FPGAsingle stuck-at faultdesign for testability
 Summary | Full Text:PDF

Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1157-1164
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
concurrent testingSOC testingtest cost reductiontest data compression
 Summary | Full Text:PDF

Scan Design for Two-Pattern Test without Extra Latches
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12  pp. 2777-2785
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testingdelay fault testingscan designenhanced scan
 Summary | Full Text:PDF

Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/09/01
Vol. E88-D  No. 9  pp. 2135-2142
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testingadjacency testdeterministic test generationBIST
 Summary | Full Text:PDF

X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1662-1670
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SOC testingtest cost reductiontest data compressionunknown statetest diagnosis
 Summary | Full Text:PDF

Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/05/01
Vol. E88-D  No. 5  pp. 984-992
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
hybrid pattern BISTcore testingtest cost reductionFPGA corereconfigurable system-on-a-chip
 Summary | Full Text:PDF

Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks
Toshinori TAKABATAKE Masato KITAKAMI Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/05/01
Vol. E85-D  No. 5  pp. 824-832
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
interconnection networksuspensive deadlock recoveryfault-tolerant routingescaperestoration
 Summary | Full Text:PDF

FOREWORD
Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/11/01
Vol. E84-D  No. 11  pp. 1451-1451
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF

Fault-Tolerant Routing Algorithms for Hypercube Interconnection Networks
Keiichi KANEKO Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/01/01
Vol. E84-D  No. 1  pp. 121-128
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
hypercube interconnection networksfault-tolerant routingfull reachabilityHamming distancecommunication
 Summary | Full Text:PDF

HCC: Generalized Hierarchical Completely-Connected Networks
Toshinori TAKABATAKE Keiichi KANEKO Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/06/25
Vol. E83-D  No. 6  pp. 1216-1224
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
interconnection networksgeneralized network, hierarchical networkcompletely-connected networkrouting strategy
 Summary | Full Text:PDF

Fast Testable Design for SRAM-Based FPGAs
Abderrahim DOUMAR Toshiaki OHMAMEUDA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5  pp. 1116-1127
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
field programmable gate array (FPGA)testingdesign for testingshifting configurations
 Summary | Full Text:PDF

Defect and Fault Tolerance SRAM-Based FPGAs by Shifting the Configuration Data
Abderrahim DOUMAR Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5  pp. 1104-1115
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
defect tolerancefault tolerancefield programmable gate array (FPGA)shifting configurations datayield improvement
 Summary | Full Text:PDF

Dynamic Constructive Fault Tolerant Algorithm for Feedforward Neural Networks
Nait Charif HAMMADI Toshiaki OHMAMEUDA Keiichi KANEKO Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/01/25
Vol. E81-D  No. 1  pp. 115-123
Type of Manuscript:  PAPER
Category: Bio-Cybernetics and Neurocomputing
Keyword: 
feedforward neural networkdynamic constructive algorithmfault toleranceDCFTA
 Summary | Full Text:PDF

On the Activation Function and Fault Tolerance in Feedforward Neural Networks
Nait Charif HAMMADI Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/01/25
Vol. E81-D  No. 1  pp. 66-72
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
feedforward neural networkXOR problemcritical weightsfault tolerancegeneralization ability
 Summary | Full Text:PDF

Detection of Fine lron Particles in High Speed Scrolled Wire by High-Tc SQUID
Hideo ITOZAKI Tatsuoki NAGAISHI Haruhisa TOYODA Hirokazu KUGAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/10/25
Vol. E80-C  No. 10  pp. 1247-1251
Type of Manuscript:  INVITED PAPER (Special Issue on Basic Properties and Applications of Superconductive Electron Devices)
Category: 
Keyword: 
high-Tc SQUIDlarge washerflux transformernondestructive evaluation
 Summary | Full Text:PDF

Automatic Adjustment of Delay Time and Feedback Gain in Delayed Feedback Control of Chaos
Hiroyuki NAKAJIMA Hideo ITO Yoshisuke UEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/09/25
Vol. E80-A  No. 9  pp. 1554-1559
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
chaoscontroldelay timefeedbackgradient descent
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A Learning Algorithm for Fault Tolerant Feedforward Neural Networks
Nait Charif HAMMADI Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1  pp. 21-27
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Redundancy Techniques
Keyword: 
feedforward neural networklearning algorithmrelevance of synaptic weightsessential linkopen faults
 Summary | Full Text:PDF

High-Tc Superconducting Quantum Interference Device with Additional Positive Feedback
Akira ADACHI Ken'ichi OKAJIMA Youichi TAKADA Saburo TANAKA Hideo ITOZAKI Haruhisa TOYODA Hisashi KADO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/05/25
Vol. E78-C  No. 5  pp. 519-525
Type of Manuscript:  Special Section PAPER (Special Issue on Superconducting Electronics and Its Applications)
Category: SQUID sensor and multi-channel SQUID system
Keyword: 
high-Tc dc-SQUIDadditional positive feedbackdirect offset integration techniqueeffective flux-to-voltage transfer functionmagnetic field noise
 Summary | Full Text:PDF

Multi-Channel SQUID
Hisashi KADO Gen UEHARA Hisanao OGATA Hideo ITOZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/05/25
Vol. E78-C  No. 5  pp. 511-518
Type of Manuscript:  INVITED PAPER (Special Issue on Superconducting Electronics and Its Applications)
Category: SQUID sensor and multi-channel SQUID system
Keyword: 
SQUIDbiomagnetismELLdewarmagnetically shielded roominverse problemmagnetic source localization
 Summary | Full Text:PDF

Multi-Channel High Tc SQUID
Hideo ITOZAKI Saburo TANAKA Tatsuoki NAGAISHI Hisashi KADO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8  pp. 1185-1190
Type of Manuscript:  INVITED PAPER (Special Section on Superconducting Devices)
Category: HTS
Keyword: 
super conductive electronicshigh Tc superconductorSQUIDstep edge junctionbiomagnetic signalsmagnetocardiogram
 Summary | Full Text:PDF

Interconnection Architecture Based on Beam-Steering Devices
Hideo ITOH Seiji MUKAI Hiroyoshi YAJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/01/25
Vol. E77-C  No. 1  pp. 15-22
Type of Manuscript:  INVITED PAPER (Special Issue on Optical Interconnection)
Category: 
Keyword: 
optical interconnectionoptical busoptical linkbeam-scanningfringe-shiftingtwin-striped laser diode
 Summary | Full Text:PDF

Array Structure Using Basic Wiring Channels for WSI Hypercube
Hideo ITO  
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6  pp. 884-893
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
wafer-scale integrationhypercubearraybasic channeldefect
 Summary | Full Text:PDF

A 2-Rail Logic Combinational Circuit for Easy Detection of Stuck-Open and Stuck-On Faults in FETs
Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6  pp. 894-901
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
easily testable designCMOSstuck-open faultstuck-on fault2-rail logic
 Summary | Full Text:PDF

High Tc Superconducting Microwave Passive Components
Kenjiro HIGAKI Hideo ITOZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/08/25
Vol. E75-C  No. 8  pp. 883-887
Type of Manuscript:  Special Section PAPER (Special Issue on Cryogenic Microwave Devices)
Category: Passive Devices
Keyword: 
high Tc superconductorsuperconducting microwave component
 Summary | Full Text:PDF

Large Scale Rectangular Grids in Hypercubes: An Embedding Scheme and Its Evaluation
M. A. Amaral HENRIQUES Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1991/06/25
Vol. E74-D  No. 6  pp. 1705-1714
Type of Manuscript:  PAPER
Category: Software Systems
Keyword: 
 Summary | Full Text:PDF

Self-Checking Checker Designs for Various 2-Rail Codes
Hideo ITOH Matsuroh NAKAMICHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1982/11/25
Vol. E65-E  No. 11  pp. 665-671
Type of Manuscript:  PAPER
Category: Digital Circuits
Keyword: 
 Summary | Full Text:PDF