Hideki YAMAUCHI


A Single-Chip JPEG2000 Encode Processor Capable of Compressing D1-Images at 30 frames/s without Tile Division
Hideki YAMAUCHI Shigeyuki OKADA Kazuhiko TAKETA Tatsushi OHYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 448-456
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
JPEG2000waveletsystem LSIimage compressionmultimedia
 Summary | Full Text:PDF

VLSI Architecture for Real-Time Fractal Image Coding Processors
Hideki YAMAUCHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/03/25
Vol. E83-A  No. 3  pp. 452-458
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
VLSI architectureimage codingfractal compression
 Summary | Full Text:PDF