Hideki HASEGAWA


Future of Heterostructure Microelectronics and Roles of Materials Research for Its Progress
Hideki HASEGAWA Seiya KASAI Taketomo SATO Tamotsu HASHIZUME 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/07/01
Vol. E89-C  No. 7  pp. 874-882
Type of Manuscript:  INVITED PAPER (Special Section on Heterostructure Microelectronics with TWHM2005)
Category: 
Keyword: 
heterostructureIII-V semiconductorsnanotechnologyhigh speed devicessensorssmart chips
 Summary | Full Text:PDF

Hexagonal Binary Decision Diagram Quantum Circuit Approach for Ultra-Low Power III-V Quantum LSIs
Hideki HASEGAWA Seiya KASAI Taketomo SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1757-1768
Type of Manuscript:  INVITED PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
quantum LSIquantum devicesbinary decision diagram (BDD)nanostructure networkintelligent quantum (IQ) chip
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Gate Leakage in AlGaN/GaN Heterostructure Field Effect Transistors and Its Suppression by Novel Al2O3 Insulated Gate
Shinya OOTOMO Hideki HASEGAWA Tamotsu HASHIZUME 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/10/01
Vol. E86-C  No. 10  pp. 2043-2050
Type of Manuscript:  Special Section PAPER (Special Issue on Heterostructure Microelectronics with TWHM2003)
Category: 
Keyword: 
GaNAlGaNleakage currentsurface statespassivation
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Surface Passivation Process for GaN-Based Electronic Devices Utilizing ECR-CVD SiNx Film
Tamotsu HASHIZUME Ryuusuke NAKASAKI Shin-ya OOTOMO Susumu OYAMA Hideki HASEGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/10/01
Vol. E84-C  No. 10  pp. 1455-1461
Type of Manuscript:  Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Novel Electron Devices
Keyword: 
GaNpassivationsurfaceSiNxECR
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Fabrication and Characterization of InGaAs/InAlAs Insulated Gate Pseudomorphic HEMTs Having a Silicon Interface Control Layer
Yong-Gui XIE Seiya KASAI Hiroshi TAKAHASHI Chao JIANG Hideki HASEGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/10/01
Vol. E84-C  No. 10  pp. 1335-1343
Type of Manuscript:  Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Hetero-FETs & Their Integrated Circuits
Keyword: 
insulated gatePHEMTInGaAsinterface controlFermi level pinning
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Process Characterization and Optimization for a Novel Oxide-Free Insulated Gate Structure for InP MISFETs Having Silicon Interface Control Layer
Hiroshi TAKAHASHI Masatsugu YAMADA Yong-Gui XIE Seiya KASAI Hideki HASEGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/10/01
Vol. E84-C  No. 10  pp. 1344-1349
Type of Manuscript:  Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Hetero-FETs & Their Integrated Circuits
Keyword: 
InPMISFETXPSC-V
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Material and Device Technology towards Quantum LSIs
Hideki HASEGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1045-1055
Type of Manuscript:  INVITED PAPER (Special Issue on New Architecture LSIs)
Category: 
Keyword: 
quantrm LSInew architecture LSI quantum devicessingle electron devices
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