IEICE Trans

Hideharu AMANO

Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud) Kazuei HIRONAKA Kensuke IIZUKA Miho YAMAKURA Akram BEN AHMED Hideharu AMANO
Publication: Publication Date: 2021/08/01 Vol. E104-D No. 8 pp. 1321-1331 Type of Manuscript: PAPER Category: Computer System Keyword: multi FPGA system, FPGA in cloud computing, interconnection networks, warehouse-scale computing, data centers,
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Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures Takeharu IKEZOE Takuya KOJIMA Hideharu AMANO
Publication: Publication Date: 2021/06/01 Vol. E104-C No. 6 pp. 215-225 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: CGRA, configuration reduction, non-volatile memory, fault-tolerance,
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Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks Ryuta KAWANO Ryota YASUDO Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: Publication Date: 2020/12/01 Vol. E103-D No. 12 pp. 2471-2479 Type of Manuscript: Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking) Category: Computer System Keyword: interconnection networks, warehouse-scale computing, data centers,
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FiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks Yuxi SUN Hideharu AMANO
Publication: Publication Date: 2020/12/01 Vol. E103-D No. 12 pp. 2457-2462 Type of Manuscript: Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking) Category: Computer System Keyword: multi-FPGA, recurrent neural networks, LSTM,
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A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks Ryuta KAWANO Ryota YASUDO Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: Publication Date: 2020/01/01 Vol. E103-D No. 1 pp. 101-110 Type of Manuscript: PAPER Category: Computer System Keyword: interconnection networks, deadlock-free routing algorithm, high performance computing, irregular networks, virtual channels,
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A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures Takuya KOJIMA Hideharu AMANO
Publication: Publication Date: 2019/07/01 Vol. E102-D No. 7 pp. 1247-1256 Type of Manuscript: PAPER Category: Computer System Keyword: CGRA, configuration reduction, integer-linear-program, multicasting,
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Proxy Responses by FPGA-Based Switch for MapReduce Stragglers Koya MITSUZUKA Michihiro KOIBUCHI Hideharu AMANO Hiroki MATSUTANI
Publication: Publication Date: 2018/09/01 Vol. E101-D No. 9 pp. 2258-2268 Type of Manuscript: PAPER Category: Computer System Keyword: FPGA, MapReduce, straggler,
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Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures Takuya KOJIMA Naoki ANDO Hayate OKUHARA Ng. Anh Vu DOAN Hideharu AMANO
Publication: Publication Date: 2018/06/01 Vol. E101-D No. 6 pp. 1532-1540 Type of Manuscript: PAPER Category: Computer System Keyword: CGRA, body bias, power reduction, Cool Mega Array,
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Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach Carlos Cesar CORTES TORRES Hayate OKUHARA Nobuyuki YAMASAKI Hideharu AMANO
Publication: Publication Date: 2018/04/01 Vol. E101-D No. 4 pp. 1116-1125 Type of Manuscript: PAPER Category: Computer System Keyword: silicon-on-insulator, SOTB, body bias, low power design, time-overhead, energy-overhead,
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A Layout-Oriented Routing Method for Low-Latency HPC Networks Ryuta KAWANO Hiroshi NAKAHARA Ikki FUJIWARA Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: Publication Date: 2017/12/01 Vol. E100-D No. 12 pp. 2796-2807 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Interconnection networks Keyword: high performance computing, network topology, interconnection networks,
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Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator Yusuke MATSUSHITA Hayate OKUHARA Koichiro MASUYAMA Yu FUJITA Ryuta KAWANO Hideharu AMANO
Publication: Publication Date: 2017/12/01 Vol. E100-D No. 12 pp. 2828-2836 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Architecture Keyword: CGRA, body bias, power reduction, cool mega array,
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A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing Ryuta KAWANO Hiroshi NAKAHARA Seiichi TADE Ikki FUJIWARA Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 pp. 1798-1806 Type of Manuscript: PAPER Category: Computer System Keyword: deadlock-free routing, high performance computing, time complexity,
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Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface Hiroshi NAKAHARA Tomoya OZAKI Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/12/01 Vol. E99-D No. 12 pp. 2871-2880 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Architecture Keyword: inductive coupling interconnect, interconnection network, network on chip,
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An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications Atsushi KOSHIBA Mikiko SATO Kimiyoshi USAMI Hideharu AMANO Ryuichi SAKAMOTO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 pp. 926-935 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: energy conservation, power gating, operating system, microprocessor,
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Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems Akram BEN AHMED Hiroki MATSUTANI Michihiro KOIBUCHI Kimiyoshi USAMI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 pp. 909-917 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: Network-on-Chips, multi-Vdd, low power networks,
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A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units Atsushi KOSHIBA Motoki WADA Ryuichi SAKAMOTO Mikiko SATO Tsubasa KOSAKA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/07/01 Vol. E98-C No. 7 pp. 559-568 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: energy conservation, power gating, operating system, Linux,
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A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode Koichiro ISHIBASHI Nobuyuki SUGII Shiro KAMOHARA Kimiyoshi USAMI Hideharu AMANO Kazutoshi KOBAYASHI Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/07/01 Vol. E98-C No. 7 pp. 536-543 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: microprocessor, low power design,
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Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh Takayuki AKAMINE Mohamad Sofian ABU TALIP Yasunori OSANA Naoyuki FUJITA Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/05/01 Vol. E97-D No. 5 pp. 1225-1234 Type of Manuscript: PAPER Category: Computer System Keyword: computational fluid dynamics (CFD), field programmable gate array (FPGA), scientific computations, reconfigurable hardware, out-of-order system,
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Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs Hao ZHANG Hiroki MATSUTANI Yasuhiro TAKE Tadahiro KURODA Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/12/01 Vol. E96-D No. 12 pp. 2753-2764 Type of Manuscript: PAPER Category: Computer System Keyword: 3-D network on chip (3-D NoC), wireless, inductive-coupling, low power, on/off vertical link,
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FOREWORD Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 pp. 1581-1581 Type of Manuscript: FOREWORD Category: Keyword:
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High-Speed Fully-Adaptable CRC Accelerators Amila AKAGIC Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/06/01 Vol. E96-D No. 6 pp. 1299-1308 Type of Manuscript: PAPER Category: Computer System Keyword: reconfigurable computing, FPGAs, cyclic redundancy checks, adaptability, accelerators,
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Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design Hiroshi NAKAMURA Weihan WANG Yuya OHTA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 404-412 Type of Manuscript: INVITED PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: low-power circuit techniques, fine grained power-gating, compiler, system hierarchy cooperation,
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FOREWORD Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/12/01 Vol. E95-D No. 12 pp. 2749-2749 Type of Manuscript: FOREWORD Category: Keyword:
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Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA Mohamad Sofian ABU TALIP Takayuki AKAMINE Yasunori OSANA Naoyuki FUJITA Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/10/01 Vol. E95-D No. 10 pp. 2369-2376 Type of Manuscript: PAPER Category: Computer System Keyword: computational fluid dynamics (CFD), field programmable gate array (FPGA), scientific computations, reconfigurable hardware, partial reconfiguration,
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FOREWORD Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 293-293 Type of Manuscript: FOREWORD Category: Keyword:
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Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor Takao TOI Takumi OKAMOTO Toru AWASHIMA Kazutoshi WAKABAYASHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2619-2627 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: coarse-grained reconfigurable architecture, dynamically reconfigurable processor, high-level synthesis, iterative synthesis, wire delay,
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A Leakage Efficient Instruction TLB Design for Embedded Processors Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/08/01 Vol. E94-D No. 8 pp. 1565-1574 Type of Manuscript: PAPER Category: Computer System Keyword: leakage power, TLB, embedded processor,
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A Leakage Efficient Data TLB Design for Embedded Processors Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/01/01 Vol. E94-D No. 1 pp. 51-59 Type of Manuscript: PAPER Category: Computer System Keyword: leakage power, TLB, embedded processor,
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Code Compression with Split Echo Instructions Iver STUBDAL Arda KARADUMAN Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/09/01 Vol. E92-D No. 9 pp. 1650-1656 Type of Manuscript: PAPER Category: Fundamentals of Software and Theory of Programs Keyword: code size, echo instructions, compression, MIPS processor,
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A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/04/01 Vol. E92-D No. 4 pp. 575-583 Type of Manuscript: PAPER Category: VLSI Systems Keyword: network-on-chip, FPGA, customize, router,
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A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors Vu Manh TUAN Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/12/01 Vol. E91-D No. 12 pp. 2793-2803 Type of Manuscript: PAPER Category: Computer Systems Keyword: dynamically reconfigurable processor, preemption algorithm, preemption latency, hardware overhead,
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A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays Vasutan TUNBUNHENG Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/11/01 Vol. E91-D No. 11 pp. 2655-2665 Type of Manuscript: PAPER Category: VLSI Systems Keyword: dynamically reconfigurable system, retargetable compiler,
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A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors Vu MANH TUAN Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/09/01 Vol. E91-D No. 9 pp. 2312-2322 Type of Manuscript: PAPER Category: Computer Systems Keyword: dynamically reconfigurable processor, multi-process execution, single-process execution,
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A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1914-1922 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable System and Applications Keyword: Networks-on-Chip, FPGA, router, port combination,
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Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices Vasutan TUNBUNHENG Masayasu SUZUKI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/02/01 Vol. E90-D No. 2 pp. 473-481 Type of Manuscript: PAPER Category: Computer Systems Keyword: dynamically reconfigurable system, high speed configuration, configuration network,
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A Survey on Dynamically Reconfigurable Processors Hideharu AMANO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2006/12/01 Vol. E89-B No. 12 pp. 3179-3187 Type of Manuscript: INVITED PAPER (Special Section on Software Defined Radio Technology and Its Applications) Category: Keyword: dynamically reconfigurable processors,
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MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing Michihiro KOIBUCHI Akiya JOURAKU Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/01/01 Vol. E88-D No. 1 pp. 109-118 Type of Manuscript: PAPER Category: Computer Systems Keyword: output selection function, adaptive routing, virtual channel, interconnection networks, massively parallel computers,
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An FPGA-Based Acceleration Method for Metabolic Simulation Yasunori OSANA Tomonori FUKUSHIMA Masato YOSHIMI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/08/01 Vol. E87-D No. 8 pp. 2029-2037 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Recornfigurable Systems Keyword: metabolic simulation, ordinary differential equations, FPGA,
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A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor Hideharu AMANO Akiya JOURAKU Kenichiro ANJO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2003/12/01 Vol. E86-B No. 12 pp. 3385-3391 Type of Manuscript: INVITED PAPER (Special Issue on Software Defined Radio Technology and Its Applications) Category: Keyword: dynamically reconfigurable systems, interconnection network,
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Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing Hiroaki NISHI Shinji NISHIMURA Katsuyoshi HARASAWA Tomohiro KUDOH Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/10/01 Vol. E86-D No. 10 pp. 1987-1995 Type of Manuscript: Special Section PAPER (Special Issue on Development of Advanced Computer Systems) Category: Keyword: RHiNET, cluster computing network, high-performance system, flow control,
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Pot: A General Purpose Monitor for Parallel Computers Yuso KANAMORI Oki MINABE Masaki WAKABAYASHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/10/01 Vol. E86-D No. 10 pp. 2025-2033 Type of Manuscript: Special Section PAPER (Special Issue on Development of Advanced Computer Systems) Category: Keyword: parallel architectures, software development environment, monitoring system,
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Performance Evaluation of Instruction Set Architecture of MBP-Light in JUMP-1 Noriaki SUZUKI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/10/01 Vol. E86-D No. 10 pp. 1996-2005 Type of Manuscript: Special Section PAPER (Special Issue on Development of Advanced Computer Systems) Category: Keyword: CC-NUMA, DSM management, instruction set architecture,
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Implementation of Data Driven Applications on a Multi-Context Reconfigurable Device Masaki UNO Yuichiro SHIBATA Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 841-849 Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing) Category: Keyword: reconfigurable machines, data driven control,
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Design and Implementation of RHiNET-2/NI0: A Reconfigurable Network Interface for Cluster Computing Tomonori YOKOYAMA Naoyuki IZU Jun-ichiro TSUCHIYA Konosuke WATANABE Hideharu AMANO Tomohiro KUDOH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 789-795 Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing) Category: Keyword: reconfigurable machines, network interface, system area network,
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A Routing Algorithm for Multihop WDM Ring Xiaoshe DONG Tomohiro KUDOH Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/02/25 Vol. E82-D No. 2 pp. 422-430 Type of Manuscript: PAPER Category: Computer Networks Keyword: interconnection network, optical communication, wavelength division multiplexing (WDM), parallel machine, routing algorithm,
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Wavelength Division Multiple Access Ring -- Virtual Topology on a Simple Ring Network -- Xiaoshe DONG Tomohiro KUDOH Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/04/25 Vol. E81-D No. 4 pp. 345-354 Type of Manuscript: PAPER Category: Computer Systems Keyword: interconnection network, optical communication, wavelength division multiple access (WDMA), parallel machine, routing algorithm,
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The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory Hiroaki NISHI Ken-ichiro ANJO Tomohiro KUDOH Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/09/25 Vol. E80-D No. 9 pp. 854-862 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Interconnection Networks Keyword: router, interconnection network, cache coherent distributed shared memory,
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MINC: Multistage Interconnection Network with Cache Control Mechanism Toshihiro HANAWA Takayuki KAMEI Hideki YASUKAWA Katsunobu NISHIMURA Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/09/25 Vol. E80-D No. 9 pp. 863-870 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Interconnection Networks Keyword: MIN, coherent cache, directory scheme, multiprocessor, congestion analysis, VLSI implementation,
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Fault Tolerance of the TBSF (Tandem Banyan Switching Fabrics) and PBSF (Piled Banyan Switching Fabrics) Akira FUNAHASHI Toshihiro HANAWA Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/08/25 Vol. E79-D No. 8 pp. 1180-1189 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Fault Diagnosis/Tolerance Keyword: Multistage Interconnection Network (MIN), MIN with multiple outlets, fault tolerance,
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The MDX (Multi-Dimensional X'bar): A Class of Networks for Large Scale Multiprocessors Atsushi MURATA Taisuke BOKU Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/08/25 Vol. E79-D No. 8 pp. 1116-1123 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Interconnection Networks Keyword: interconnection network, crossbar, MIN, multiprocessors,
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Message Transfer Algorithms on the Recursive Diagonal Torus Yulu YANG Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/02/25 Vol. E79-D No. 2 pp. 107-116 Type of Manuscript: PAPER Category: Computer Systems Keyword: interconnection network, routing algorithm, broadcast, deadlock-free,
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A Batcher-Double-Omega Network with Combining Kalidou GAYE Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/05/25 Vol. E75-D No. 3 pp. 307-314 Type of Manuscript: PAPER Category: Computer Networks Keyword: Interconnection networks, multiprocessors, message combining,
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The Compatible Acknowledging Ethernet Toshitada SAITO Mario TOKORO Hideharu AMANO
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/10/25 Vol. E70-E No. 10 pp. 960-967 Type of Manuscript: PAPER Category: Switching and Communication Processing Keyword:
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A VLSI Switch for a Digital PBX Suhut Hasiholan PURBA Hideharu AMANO Yasuro SHOBATAKE Hideo AISO
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1986/07/25 Vol. E69-E No. 7 pp. 771-774 Type of Manuscript: LETTER Category: Switching Systems and Communication Processing Keyword:
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