Hayato MASHIKO


Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning
Kota MUROI Hayato MASHIKO Yukihide KOHIRA 
Publication:   
Publication Date: 2019/07/01
Vol. E102-A  No. 7  pp. 894-903
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
post-silicon delay tuningprogrammable delay elementyield improvementpower consumption reduction
 Summary | Full Text:PDF(1.1MB)

Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework
Junki KAWAGUCHI Hayato MASHIKO Yukihide KOHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1366-1373
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
general-synchronous frameworktechnology mappinginteger linear programming
 Summary | Full Text:PDF(753.4KB)

A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement
Hayato MASHIKO Yukihide KOHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2443-2450
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
delay variationtiming violationyieldprogrammable delay element
 Summary | Full Text:PDF(1.1MB)