Haruka SASAKI

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture
Masanori HARIYAMA Yasuhiro KOBAYASHI Haruka SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3516-3522
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
stereo vision, FPGA, scheduling, allocation, 
 Summary | Full Text:PDF(812.1KB)
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access
Masanori HARIYAMA Haruka SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1486-1491
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
stereo vision, SAD (sum of absolute differences), memory allocation, logic-in-memory architecture, 
 Summary | Full Text:PDF(1.1MB)