Hanho LEE


A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications
Jeong-In PARK Hanho LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2424-2429
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Reed-Solomonforward error correctiontime-multiplexingtruncated inversionless Berlekamp-Masseyoptical communications
 Summary | Full Text:PDF

Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications
Kisun JUNG Hanho LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11  pp. 2376-2383
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
DVB-T2FFTmulti-modescalingpipelinedshared memory
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High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems
Chang-Seok CHOI Hyo-Jin AHN Hanho LEE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/05/01
Vol. E94-B  No. 5  pp. 1332-1338
Type of Manuscript:  PAPER
Category: Network
Keyword: 
forward error correction (FEC)Reed-Solomon (RS)decodermmWAVEWPAN
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Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems
Yong-Kyu KIM Chang-Seok CHOI Hanho LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/03/01
Vol. E94-A  No. 3  pp. 937-945
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
digital signal processing (DSP)FIRfilterarchitecturecubic splineinterpolationdigital TV (DTV)
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High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications
Sangho YOON Hanho LEE Kihoon LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/04/01
Vol. E93-A  No. 4  pp. 769-777
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
concatenated BCH codeFECarchitectureoptical
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A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems
Jeesung LEE Hanho LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1206-1211
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Fast Fourier transform (FFT)radix-24SDFmultiband orthogonal frequency-division multiplexing (MB-OFDM)ultrawideband (UWB)
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A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders
Seungbeom LEE Hanho LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/03/01
Vol. E91-A  No. 3  pp. 830-835
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Reed-Solomon (RS) codesdegree-computationlessmodified Eulclideansystolic array
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A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform
Chang-Seok CHOI Hanho LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12  pp. 1932-1938
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
partial reconfigurationself-reconfigurationadaptive FIR filterFPGA
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A Design and Performance of 4-Parallel MB-OFDM UWB Receiver
Cheol-Ho SHIN Sangsung CHOI Hanho LEE Jeong-Ki PACK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/03/01
Vol. E90-B  No. 3  pp. 672-675
Type of Manuscript:  LETTER
Category: Wireless Communication Technologies
Keyword: 
MB-OFDMUWBparallel structuresynchronization
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Power-Aware Scalable Pipelined Booth Multiplier
Hanho LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A  No. 11  pp. 3230-3234
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
power-awarepipelinedBooth multiplierlow-powerdesign
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