Hajime SHIMADA


Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences
Ryotaro KOBAYASHI Ikumi KANEKO Hajime SHIMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/08/01
Vol. E99-C  No. 8  pp. 936-946
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
cache memorylow powerfrequent bit sequences
 Summary | Full Text:PDF(799.9KB)

BTB Energy Reduction by Focusing on Useless Accesses
Yoshio SHIMOMURA Hiroki YAMAMOTO Hayato USUI Ryotaro KOBAYASHI Hajime SHIMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 569-579
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
Branch Target Bufferbranch predictionenergy reduction
 Summary | Full Text:PDF(771.4KB)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing
Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Hajime SHIMADA Kazutoshi KOBAYASHI Hiroyuki KANBARA Hiroyuki OCHI Takashi IMAGAWA Kazutoshi WAKABAYASHI Masanori HASHIMOTO Takao ONOYE Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2518-2529
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
reconfigurable architecturesoft errorradiation testbehavioral synthesisstate machine
 Summary | Full Text:PDF(3.8MB)

An Instruction Mapping Scheme for FU Array Accelerator
Kazuhiro YOSHIMURA Takuya IWAKAMI Takashi NAKADA Jun YAO Hajime SHIMADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/02/01
Vol. E94-D  No. 2  pp. 286-297
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
instruction mappingFU arraycoarse-grained reconfigurable architecture
 Summary | Full Text:PDF(3.6MB)

A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases
Jun YAO Shinobu MIWA Hajime SHIMADA Shinji TOMITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/04/01
Vol. E91-D  No. 4  pp. 1010-1022
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
energy savingdynamic optimizationpipeline stage unificationprogram phase
 Summary | Full Text:PDF(923.7KB)