Hafiz Md. HASAN BABU

Heuristics to Minimize Multiple-Valued Decision Diagrams
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2498-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
binary decision diagram (BDD), multiple-valued decision diagram (MDD), multiple-output function, multiple-valued logic, FPGA design, 
 Summary | Full Text:PDF(451.2KB)
Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2398-2406
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagram (BDD), characteristic function (CF), multiple-output function, variable ordering, logic simulation, adder, bit-counting function, multiplier, 
 Summary | Full Text:PDF(563.6KB)
Time-Division Multiplexing Realizations of Multiple-Output Functions Based on Shared Multi-Terminal Multiple-Valued Decision Diagrams
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5  pp. 925-932
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications)
Category: Logic Design
Keyword: 
multiple-valued decision diagram (MDD), multiple-valued logic, multiple-output function, time-division multiplexing (TDM), 
 Summary | Full Text:PDF(411.7KB)
Shared Multi-Terminal Binary Decision Diagrams for Multiple-Output Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2545-2553
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
binary decision diagram (BDD), multiple-output functions,  clique cover, TDM realization, logic simulation, 
 Summary | Full Text:PDF(652.7KB)