Guifen TIAN


Dynamic Check Message Majority-Logic Decoding Algorithm for Non-binary LDPC Codes
Yichao LU Xiao PENG Guifen TIAN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/06/01
Vol. E97-A  No. 6  pp. 1356-1364
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
non-binary LDPC codesmajority-logic decodingiterative decodingmessage-passing algorithms
 Summary | Full Text:PDF(1.4MB)

Hybrid Message-Passing Algorithm and Architecture for Decoding Cyclic Non-binary LDPC Codes
Yichao LU Gang HE Guifen TIAN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2652-2659
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
Belief propagation algorithmiterative majority-logic decodinglow-density parity-check codesnon-binaryVLSI
 Summary | Full Text:PDF(1.6MB)

Content Adaptive Hierarchical Decision of Variable Coding Block Sizes in High Efficiency Video Coding for High Resolution Videos
Guifen TIAN Xin JIN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/04/01
Vol. E96-A  No. 4  pp. 780-789
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
video codingHEVCcontent adaptivevariable block sized predictionsum of absolute quantized residual coefficient
 Summary | Full Text:PDF(2.9MB)

All-Zero Block-Based Optimization for Quadtree-Structured Prediction and Residual Encoding in High Efficiency Video Coding
Guifen TIAN Xin JIN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/04/01
Vol. E96-A  No. 4  pp. 769-779
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
HEVCall-zero blockvariable block sizeresidual encoding
 Summary | Full Text:PDF(3.5MB)

High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
Tianruo ZHANG Guifen TIAN Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3630-3637
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
H.264/AVCintra predictionfast mode decision algorithmVLSI architecture
 Summary | Full Text:PDF(870.9KB)