Gang ZENG


A Genetic Algorithm for Packing CAN FD Frame with Real-Time Constraints
Shan DING Gang ZENG Ryo KURACHI Ruifeng HUANG 
Publication:   
Publication Date: 2017/10/01
Vol. E100-D  No. 10  pp. 2505-2514
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
in-vehicle networkController Area Networkframe packingnetwork bandwidthschedulability
 Summary | Full Text:PDF(1.3MB)

An Integrated Framework for Energy Optimization of Embedded Real-Time Applications
Hideki TAKASE Gang ZENG Lovic GAUTHIER Hirotaka KAWASHIMA Noritoshi ATSUMI Tomohiro TATEMATSU Yoshitake KOBAYASHI Takenori KOSHIRO Tohru ISHIHARA Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2477-2487
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
energy optimizationcompilerprofilerreal-time operating systemsembedded systems
 Summary | Full Text:PDF(7.3MB)

Worst Case Response Time Analysis for Messages in Controller Area Network with Gateway
Yong XIE Gang ZENG Yang CHEN Ryo KURACHI Hiroaki TAKADA Renfa LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/07/01
Vol. E96-D  No. 7  pp. 1467-1477
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
CANgatewaybusy sequenceworst case response timethe minimum distance constraint
 Summary | Full Text:PDF(1.1MB)

Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems
Tetsuo YOKOYAMA Gang ZENG Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/10/01
Vol. E93-D  No. 10  pp. 2737-2746
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
battery-aware voltage schedulingdynamic voltage scalinglow powerreal-time systems
 Summary | Full Text:PDF(666.6KB)

Low-Cost IP Core Test Using Tri-Template-Based Codes
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 288-295
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design for testabilityIP core testingtest cost reductiontest data compression
 Summary | Full Text:PDF(475KB)

Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1157-1164
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
concurrent testingSOC testingtest cost reductiontest data compression
 Summary | Full Text:PDF(786.2KB)

X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1662-1670
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SOC testingtest cost reductiontest data compressionunknown statetest diagnosis
 Summary | Full Text:PDF(658.4KB)

Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/05/01
Vol. E88-D  No. 5  pp. 984-992
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
hybrid pattern BISTcore testingtest cost reductionFPGA corereconfigurable system-on-a-chip
 Summary | Full Text:PDF(326.5KB)