Fumihiro MINAMI

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations
Susumu KOBAYASHI Fumihiro MINAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1980-1985
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
clock skew, interconnect, process variation, signal delay, 
 Summary | Full Text:PDF
Gate Delay Estimation in STA under Dynamic Power Supply Noise
Takaaki OKUMURA Fumihiro MINAMI Kenji SHIMAZAKI Kimihiko KUWADA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2447-2455
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
power supply noise, gate delay, timing analysis, 
 Summary | Full Text:PDF
Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays
Midori TAKANO Fumihiro MINAMI Naohito KOJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1405-1409
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
clock routing, delay, skew, embedded array, 
 Summary | Full Text:PDF