IEICE Trans

Fukashi MORISHITA

High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor Fukashi MORISHITA Wataru SAITO Norihito KATO Yoichi IIZUKA Masao ITO
Publication: Publication Date: 2022/07/01 Vol. E105-C No. 7 pp. 316-323 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: CMOS image sensor, column-parallel ADC, ramp generator, multi-functional fine pattern generator, IP test,
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On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform Hiroki SHIMANO Fukashi MORISHITA Katsumi DOSAKA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/03/01 Vol. E92-C No. 3 pp. 356-363 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: power management, low voltage scalability, SoC memory platform,
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A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform Hiroki SHIMANO Fukashi MORISHITA Katsumi DOSAKA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1927-1935 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Next-Generation Memory for SoC Keyword: DFM RAM, 2 cell/bit, low voltage scalability, screening test, SoC memory platform,
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A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI Fukashi MORISHITA Hideyuki NODA Isamu HAYASHI Takayuki GYOHTEN Mako OKAMOTO Takashi IPPOSHI Shigeto MAEGAWA Katsumi DOSAKA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 765-771 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: SOI, capacitorless, DRAM, low power, data retention,
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An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design Takayuki GYOHTEN Fukashi MORISHITA Isamu HAYASHI Mako OKAMOTO Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Yasutaka HORIBA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1519-1525 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: PVT variation, temperature detection, series regulator,
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A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC Hideyuki NODA Katsumi DOSAKA Hans Jurgen MATTAUSCH Tetsushi KOIDE Fukashi MORISHITA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1612-1619 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: soft error, ECC, TCAM, embedded, DRAM,
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A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros Akira YAMAZAKI Fukashi MORISHITA Naoya WATANABE Teruhiko AMANO Masaru HARAGUCHI Hideyuki NODA Atsushi HACHISUKA Katsumi DOSAKA Kazutami ARIMOTO Setsuo WAKE Hideyuki OZAKI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/10/01 Vol. E88-C No. 10 pp. 2020-2027 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: embedded memory, DRAM, voltage margin, low voltage, system on chip,
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A Low Power Embedded DRAM Macro for Battery-Operated LSIs Takeshi FUJINO Akira YAMAZAKI Yasuhiko TAITO Mitsuya KINOSHITA Fukashi MORISHITA Teruhiko AMANO Masaru HARAGUCHI Makoto HATAKENAKA Atsushi AMO Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2991-3000 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Power Optimization Keyword: embedded memory, DRAM, low power, system on chip,
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An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester Naoya WATANABE Fukashi MORISHITA Yasuhiko TAITO Akira YAMAZAKI Tetsushi TANIZAKI Katsumi DOSAKA Yoshikazu MOROOKA Futoshi IGAUE Katsuya FURUE Yoshihiro NAGURA Tatsunori KOMOIKE Toshinori MORIHARA Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 624-634 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: embedded DRAM, various DRAM macros, low voltage operation, short TAT, BIST,
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A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/09/01 Vol. E85-C No. 9 pp. 1697-1708 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: embedded DRAM, system on chip, 3-D graphics concurrent operation,
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Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs Fukashi MORISHITA Kazutami ARIMOTO Kazuyasu FUJISHIMA Hideyuki OZAKI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 253-259 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SOI, floating body, body control, high speed, low power,
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Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM Fukashi MORISHITA Yasuo YAMAGUCHI Takahisa EIMORI Toshiyuki OASHI Kazutami ARIMOTO Yasuo INOUE Tadashi NISHIMURA Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/03/25 Vol. E82-C No. 3 pp. 544-552 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology) Category: Silicon Devices Keyword: SOI-DRAM, floating body, high speed, low power, data retention characteristics,
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A Long Data Retention SOI DRAM with the Body Refresh Function Shigeki TOMISHIMA Fukashi MORISHITA Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 899-904 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Novel Structure Devices Keyword: memory, SOI-DRAM, body region, refresh, data retention,
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SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories Shigehiro KUGE Fukashi MORISHITA Takahiro TSURUDA Shigeki TOMISHIMA Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/25 Vol. E79-C No. 7 pp. 997-1002 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
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Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's Yasuo YAMAGUCHI Toshiyuki OASHI Takahisa EIMORI Toshiaki IWAMATSU Shouichi MITAMOTO Katsuhiro SUMA Takahiro TSURUDA Fukashi MORISHITA Masakazu HIROSE Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Yasuo INOUE Tadashi NISHIMURA Hirokazu MIYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 pp. 772-780 Type of Manuscript: INVITED PAPER (Special Issue on ULSI Memory Technology) Category: Dynamic RAMs Keyword: SOL, SIMOX, DRAM, low-voltage operation,
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