Euiseok KIM


Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design
Nattha SRETASEREEKUL Hiroshi SAITO Euiseok KIM Metehan OZCAN Masashi IMAI Hiroshi NAKAMURA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3028-3037
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
asynchronous controllerslogic synthesisControl Data Flow Graphs (CDFGs)Signal Transition Graphs (STGs)
 Summary | Full Text:PDF(801.7KB)

Automatic Process-Oriented Asynchronous Control Unit Generation from Control Data Flow Graphs
Euiseok KIM Jeong-Gun LEE Dong-Ik LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A  No. 8  pp. 2014-2028
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
automatic asynchronous control unit generationprocess-orientedcontrol data flow graphssignal transition graph
 Summary | Full Text:PDF(1.6MB)