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Copyright (c) by IEICE
Erl-Huei LU
An Efficient Weighted Bit-Flipping Algorithm for Decoding LDPC Codes Based on Log-Likelihood Ratio of Bit Error Probability
Tso-Cho CHEN
Erl-Huei LU
Chia-Jung LI
Kuo-Tsang HUANG
Publication:
Publication Date:
2017/12/01
Vol.
E100-B
No.
12
pp.
2095-2103
Type of Manuscript:
PAPER
Category:
Fundamental Theories for Communications
Keyword:
low-density parity-check codes
,
weighted bit-flipping
,
multiple bit-flipping
,
decoding algorithm
,
log-likelihood ratio
,
convergence speed
,
Summary
|
Full Text:PDF
Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder
Ya-Cheng LU
Erl-Huei LU
Publication:
IEICE TRANSACTIONS on Communications
Publication Date:
2010/01/01
Vol.
E93-B
No.
1
pp.
1-8
Type of Manuscript:
PAPER
Category:
Fundamental Theories for Communications
Keyword:
concurrent decoding
,
turbo codes
,
maximum a posteriori (MAP)
,
iterative decoding delay
,
low latency
,
Summary
|
Full Text:PDF
Scalable and Systolic Montgomery Multipliers over GF(2
m
)
Chin-Chin CHEN
Chiou-Yng LEE
Erl-Huei LU
Publication:
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date:
2008/07/01
Vol.
E91-A
No.
7
pp.
1763-1771
Type of Manuscript:
PAPER
Category:
VLSI Design Technology and CAD
Keyword:
systolic multiplier
,
Toeplitz matrix-vector
,
scalable architecture
,
Montgomery
,
Summary
|
Full Text:PDF