Eiji IKAWA


0.15 µm CMOS Devices with Reduced Junction Capacitance
Akira TANABE Kiyoshi TAKEUCHI Toyoji YAMAMOTO Takeo MATSUKI Takemitsu KUNIO Masao FUKUMA Ken NAKAJIMA Naoki AIZAKI Hidenobu MIYAMOTO Eiji IKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/03/25
Vol. E78-C  No. 3  pp. 267-273
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies)
Category: 
Keyword: 
CMOSEB lithographyTi salicideSPICE
 Summary | Full Text:PDF

A Capacitor over Bit-Line (COB) Stacked Capacitor Cell Using Local Interconnect Layer for 64 MbDRAMs
Naoki KASAI Masato SAKAO Toshiyuki ISHIJIMA Eiji IKAWA Hirohito WATANABE Toshio TAKESHIMA Nobuhiro TANABE Kazuo TERADA Takamaro KIKKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Vol. E76-C  No. 4  pp. 548-555
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
DRAMmemory cellstacked capacitorlocal interconnect
 Summary | Full Text:PDF