Dongsheng YANG

A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS
Bangan LIU Yun WANG Jian PANG Haosheng ZHANG Dongsheng YANG Aravind Tharayil NARAYANAN Dae Young LEE Sung Tae CHOI Rui WU Kenichi OKADA Akira MATSUZAWA 
Publication:   
Publication Date: 2018/02/01
Vol. E101-C  No. 2  pp. 126-134
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
60-GHz, 5G communication, spectrum mask compliant, duobinary, semi-digital FIR, 
 Summary | Full Text:PDF(2MB)
A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI
Aravind THARAYIL NARAYANAN Wei DENG Dongsheng YANG Rui WU Kenichi OKADA Akira MATSUZAWA 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 259-267
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
fully-synthesizable, all-digital, clock data recovery, injection locking, phase-filtering, 
 Summary | Full Text:PDF(3.8MB)
A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI
Dongsheng YANG Tomohiro UENO Wei DENG Yuki TERASHIMA Kengo NAKATA Aravind Tharayil NARAYANAN Rui WU Kenichi OKADA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 632-640
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
AD-PLL, synthesizable, stochastic TDC, standard cell, automatic place-and-route, 
 Summary | Full Text:PDF(2MB)