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A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine
Hsuan-Chun LIAO Mochamad ASRI Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A
No. 6
pp. 1222-1235
Type of Manuscript:
Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category:
Keyword:
ASIP, image processing, | | | Summary | Full Text:PDF | |
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A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing
Hsuan-Chun LIAO Mochamad ASRI Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12
pp. 2373-2383
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
ASIP, image processing, | | | Summary | Full Text:PDF | |
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Memory Sharing Processor Array (MSPA) Architecture
Dongju LI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A
No. 12
pp. 2086-2096
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
processor array, data-path synthesis, systolic array, | | | Summary | Full Text:PDF | |
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